// -*- mode:c++ -*-
+// Copyright (c) 2013 ARM Limited
+// All rights reserved
+//
+// The license below extends only to copyright in the software and shall
+// not be construed as granting a license to any other intellectual
+// property including but not limited to intellectual property relating
+// to a hardware implementation of the functionality of the software
+// licensed hereunder. You may use the software subject to the license
+// terms below provided that you ensure that this notice is replicated
+// unmodified and in its entirety in all distributions of the software,
+// modified or unmodified, in source code or in binary form.
+//
// Copyright (c) 2003-2006 The Regents of The University of Michigan
// All rights reserved.
//
}
format LoadOrNop {
- 0x0a: ldbu({{ Ra.uq = Mem.ub; }});
- 0x0c: ldwu({{ Ra.uq = Mem.uw; }});
- 0x0b: ldq_u({{ Ra = Mem.uq; }}, ea_code = {{ EA = (Rb + disp) & ~7; }});
- 0x23: ldt({{ Fa = Mem.df; }});
- 0x2a: ldl_l({{ Ra.sl = Mem.sl; }}, mem_flags = LOCKED);
- 0x2b: ldq_l({{ Ra.uq = Mem.uq; }}, mem_flags = LOCKED);
-#ifdef USE_COPY
- 0x20: MiscPrefetch::copy_load({{ EA = Ra; }},
- {{ fault = xc->copySrcTranslate(EA); }},
- inst_flags = [IsMemRef, IsLoad, IsCopy]);
-#endif
+ 0x0a: ldbu({{ Ra_uq = Mem_ub; }});
+ 0x0c: ldwu({{ Ra_uq = Mem_uw; }});
+ 0x0b: ldq_u({{ Ra = Mem_uq; }}, ea_code = {{ EA = (Rb + disp) & ~7; }});
+ 0x23: ldt({{ Fa = Mem_df; }});
+ 0x2a: ldl_l({{ Ra_sl = Mem_sl; }}, mem_flags = LLSC);
+ 0x2b: ldq_l({{ Ra_uq = Mem_uq; }}, mem_flags = LLSC);
}
format LoadOrPrefetch {
- 0x28: ldl({{ Ra.sl = Mem.sl; }});
- 0x29: ldq({{ Ra.uq = Mem.uq; }}, pf_flags = EVICT_NEXT);
+ 0x28: ldl({{ Ra_sl = Mem_sl; }});
+ 0x29: ldq({{ Ra_uq = Mem_uq; }}, pf_flags = EVICT_NEXT);
// IsFloating flag on lds gets the prefetch to disassemble
// using f31 instead of r31... funcitonally it's unnecessary
- 0x22: lds({{ Fa.uq = s_to_t(Mem.ul); }},
+ 0x22: lds({{ Fa_uq = s_to_t(Mem_ul); }},
pf_flags = PF_EXCLUSIVE, inst_flags = IsFloating);
}
format Store {
- 0x0e: stb({{ Mem.ub = Ra<7:0>; }});
- 0x0d: stw({{ Mem.uw = Ra<15:0>; }});
- 0x2c: stl({{ Mem.ul = Ra<31:0>; }});
- 0x2d: stq({{ Mem.uq = Ra.uq; }});
- 0x0f: stq_u({{ Mem.uq = Ra.uq; }}, {{ EA = (Rb + disp) & ~7; }});
- 0x26: sts({{ Mem.ul = t_to_s(Fa.uq); }});
- 0x27: stt({{ Mem.df = Fa; }});
-#ifdef USE_COPY
- 0x24: MiscPrefetch::copy_store({{ EA = Rb; }},
- {{ fault = xc->copy(EA); }},
- inst_flags = [IsMemRef, IsStore, IsCopy]);
-#endif
+ 0x0e: stb({{ Mem_ub = Ra<7:0>; }});
+ 0x0d: stw({{ Mem_uw = Ra<15:0>; }});
+ 0x2c: stl({{ Mem_ul = Ra<31:0>; }});
+ 0x2d: stq({{ Mem_uq = Ra_uq; }});
+ 0x0f: stq_u({{ Mem_uq = Ra_uq; }}, {{ EA = (Rb + disp) & ~7; }});
+ 0x26: sts({{ Mem_ul = t_to_s(Fa_uq); }});
+ 0x27: stt({{ Mem_df = Fa; }});
}
format StoreCond {
- 0x2e: stl_c({{ Mem.ul = Ra<31:0>; }},
+ 0x2e: stl_c({{ Mem_ul = Ra<31:0>; }},
{{
uint64_t tmp = write_result;
// see stq_c
if (tmp == 1) {
xc->setStCondFailures(0);
}
- }}, mem_flags = LOCKED, inst_flags = IsStoreConditional);
- 0x2f: stq_c({{ Mem.uq = Ra; }},
+ }}, mem_flags = LLSC, inst_flags = IsStoreConditional);
+ 0x2f: stq_c({{ Mem_uq = Ra; }},
{{
uint64_t tmp = write_result;
// If the write operation returns 0 or 1, then
// only.
xc->setStCondFailures(0);
}
- }}, mem_flags = LOCKED, inst_flags = IsStoreConditional);
+ }}, mem_flags = LLSC, inst_flags = IsStoreConditional);
}
format IntegerOperate {
- 0x10: decode INTFUNC { // integer arithmetic operations
+ 0x10: decode INTFUNC { // integer arithmetic operations
- 0x00: addl({{ Rc.sl = Ra.sl + Rb_or_imm.sl; }});
+ 0x00: addl({{ Rc_sl = Ra_sl + Rb_or_imm_sl; }});
0x40: addlv({{
- uint32_t tmp = Ra.sl + Rb_or_imm.sl;
+ int32_t tmp = Ra_sl + Rb_or_imm_sl;
// signed overflow occurs when operands have same sign
// and sign of result does not match.
- if (Ra.sl<31:> == Rb_or_imm.sl<31:> && tmp<31:> != Ra.sl<31:>)
- fault = new IntegerOverflowFault;
- Rc.sl = tmp;
+ if (Ra_sl<31:> == Rb_or_imm_sl<31:> && tmp<31:> != Ra_sl<31:>)
+ fault = std::make_shared<IntegerOverflowFault>();
+ Rc_sl = tmp;
}});
- 0x02: s4addl({{ Rc.sl = (Ra.sl << 2) + Rb_or_imm.sl; }});
- 0x12: s8addl({{ Rc.sl = (Ra.sl << 3) + Rb_or_imm.sl; }});
+ 0x02: s4addl({{ Rc_sl = (Ra_sl << 2) + Rb_or_imm_sl; }});
+ 0x12: s8addl({{ Rc_sl = (Ra_sl << 3) + Rb_or_imm_sl; }});
0x20: addq({{ Rc = Ra + Rb_or_imm; }});
0x60: addqv({{
// signed overflow occurs when operands have same sign
// and sign of result does not match.
if (Ra<63:> == Rb_or_imm<63:> && tmp<63:> != Ra<63:>)
- fault = new IntegerOverflowFault;
+ fault = std::make_shared<IntegerOverflowFault>();
Rc = tmp;
}});
0x22: s4addq({{ Rc = (Ra << 2) + Rb_or_imm; }});
0x32: s8addq({{ Rc = (Ra << 3) + Rb_or_imm; }});
- 0x09: subl({{ Rc.sl = Ra.sl - Rb_or_imm.sl; }});
+ 0x09: subl({{ Rc_sl = Ra_sl - Rb_or_imm_sl; }});
0x49: sublv({{
- uint32_t tmp = Ra.sl - Rb_or_imm.sl;
+ int32_t tmp = Ra_sl - Rb_or_imm_sl;
// signed overflow detection is same as for add,
// except we need to look at the *complemented*
// sign bit of the subtrahend (Rb), i.e., if the initial
// signs are the *same* then no overflow can occur
- if (Ra.sl<31:> != Rb_or_imm.sl<31:> && tmp<31:> != Ra.sl<31:>)
- fault = new IntegerOverflowFault;
- Rc.sl = tmp;
+ if (Ra_sl<31:> != Rb_or_imm_sl<31:> && tmp<31:> != Ra_sl<31:>)
+ fault = std::make_shared<IntegerOverflowFault>();
+ Rc_sl = tmp;
}});
- 0x0b: s4subl({{ Rc.sl = (Ra.sl << 2) - Rb_or_imm.sl; }});
- 0x1b: s8subl({{ Rc.sl = (Ra.sl << 3) - Rb_or_imm.sl; }});
+ 0x0b: s4subl({{ Rc_sl = (Ra_sl << 2) - Rb_or_imm_sl; }});
+ 0x1b: s8subl({{ Rc_sl = (Ra_sl << 3) - Rb_or_imm_sl; }});
0x29: subq({{ Rc = Ra - Rb_or_imm; }});
0x69: subqv({{
// sign bit of the subtrahend (Rb), i.e., if the initial
// signs are the *same* then no overflow can occur
if (Ra<63:> != Rb_or_imm<63:> && tmp<63:> != Ra<63:>)
- fault = new IntegerOverflowFault;
+ fault = std::make_shared<IntegerOverflowFault>();
Rc = tmp;
}});
0x2b: s4subq({{ Rc = (Ra << 2) - Rb_or_imm; }});
0x3b: s8subq({{ Rc = (Ra << 3) - Rb_or_imm; }});
0x2d: cmpeq({{ Rc = (Ra == Rb_or_imm); }});
- 0x6d: cmple({{ Rc = (Ra.sq <= Rb_or_imm.sq); }});
- 0x4d: cmplt({{ Rc = (Ra.sq < Rb_or_imm.sq); }});
- 0x3d: cmpule({{ Rc = (Ra.uq <= Rb_or_imm.uq); }});
- 0x1d: cmpult({{ Rc = (Ra.uq < Rb_or_imm.uq); }});
+ 0x6d: cmple({{ Rc = (Ra_sq <= Rb_or_imm_sq); }});
+ 0x4d: cmplt({{ Rc = (Ra_sq < Rb_or_imm_sq); }});
+ 0x3d: cmpule({{ Rc = (Ra_uq <= Rb_or_imm_uq); }});
+ 0x1d: cmpult({{ Rc = (Ra_uq < Rb_or_imm_uq); }});
0x0f: cmpbge({{
int hi = 7;
int lo = 0;
uint64_t tmp = 0;
for (int i = 0; i < 8; ++i) {
- tmp |= (Ra.uq<hi:lo> >= Rb_or_imm.uq<hi:lo>) << i;
+ tmp |= (Ra_uq<hi:lo> >= Rb_or_imm_uq<hi:lo>) << i;
hi += 8;
lo += 8;
}
}});
}
- 0x11: decode INTFUNC { // integer logical operations
+ 0x11: decode INTFUNC { // integer logical operations
0x00: and({{ Rc = Ra & Rb_or_imm; }});
0x08: bic({{ Rc = Ra & ~Rb_or_imm; }});
0x16: cmovlbc({{ Rc = ((Ra & 1) == 0) ? Rb_or_imm : Rc; }});
0x24: cmoveq({{ Rc = (Ra == 0) ? Rb_or_imm : Rc; }});
0x26: cmovne({{ Rc = (Ra != 0) ? Rb_or_imm : Rc; }});
- 0x44: cmovlt({{ Rc = (Ra.sq < 0) ? Rb_or_imm : Rc; }});
- 0x46: cmovge({{ Rc = (Ra.sq >= 0) ? Rb_or_imm : Rc; }});
- 0x64: cmovle({{ Rc = (Ra.sq <= 0) ? Rb_or_imm : Rc; }});
- 0x66: cmovgt({{ Rc = (Ra.sq > 0) ? Rb_or_imm : Rc; }});
+ 0x44: cmovlt({{ Rc = (Ra_sq < 0) ? Rb_or_imm : Rc; }});
+ 0x46: cmovge({{ Rc = (Ra_sq >= 0) ? Rb_or_imm : Rc; }});
+ 0x64: cmovle({{ Rc = (Ra_sq <= 0) ? Rb_or_imm : Rc; }});
+ 0x66: cmovgt({{ Rc = (Ra_sq > 0) ? Rb_or_imm : Rc; }});
// For AMASK, RA must be R31.
0x61: decode RA {
0x6c: decode RA {
31: decode IMM {
1: decode INTIMM {
- // return EV5 for FULL_SYSTEM and EV6 otherwise
- 1: implver({{
-#if FULL_SYSTEM
- Rc = 1;
-#else
- Rc = 2;
-#endif
- }});
+ // return EV5 for FullSystem and EV6 otherwise
+ 1: implver({{ Rc = FullSystem ? 1 : 2 }});
}
}
}
-#if FULL_SYSTEM
// The mysterious 11.25...
0x25: WarnUnimpl::eleven25();
-#endif
}
0x12: decode INTFUNC {
0x39: sll({{ Rc = Ra << Rb_or_imm<5:0>; }});
- 0x34: srl({{ Rc = Ra.uq >> Rb_or_imm<5:0>; }});
- 0x3c: sra({{ Rc = Ra.sq >> Rb_or_imm<5:0>; }});
+ 0x34: srl({{ Rc = Ra_uq >> Rb_or_imm<5:0>; }});
+ 0x3c: sra({{ Rc = Ra_sq >> Rb_or_imm<5:0>; }});
0x02: mskbl({{ Rc = Ra & ~(mask( 8) << (Rb_or_imm<2:0> * 8)); }});
0x12: mskwl({{ Rc = Ra & ~(mask(16) << (Rb_or_imm<2:0> * 8)); }});
Rc = bv ? (Ra & ~(mask(64) >> (64 - 8 * bv))) : Ra;
}});
- 0x06: extbl({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8))< 7:0>; }});
- 0x16: extwl({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8))<15:0>; }});
- 0x26: extll({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8))<31:0>; }});
- 0x36: extql({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8)); }});
+ 0x06: extbl({{ Rc = (Ra_uq >> (Rb_or_imm<2:0> * 8))< 7:0>; }});
+ 0x16: extwl({{ Rc = (Ra_uq >> (Rb_or_imm<2:0> * 8))<15:0>; }});
+ 0x26: extll({{ Rc = (Ra_uq >> (Rb_or_imm<2:0> * 8))<31:0>; }});
+ 0x36: extql({{ Rc = (Ra_uq >> (Rb_or_imm<2:0> * 8)); }});
0x5a: extwh({{
Rc = (Ra << (64 - (Rb_or_imm<2:0> * 8))<5:0>)<15:0>; }});
0x57: inswh({{
int bv = Rb_or_imm<2:0>;
- Rc = bv ? (Ra.uq<15:0> >> (64 - 8 * bv)) : 0;
+ Rc = bv ? (Ra_uq<15:0> >> (64 - 8 * bv)) : 0;
}});
0x67: inslh({{
int bv = Rb_or_imm<2:0>;
- Rc = bv ? (Ra.uq<31:0> >> (64 - 8 * bv)) : 0;
+ Rc = bv ? (Ra_uq<31:0> >> (64 - 8 * bv)) : 0;
}});
0x77: insqh({{
int bv = Rb_or_imm<2:0>;
- Rc = bv ? (Ra.uq >> (64 - 8 * bv)) : 0;
+ Rc = bv ? (Ra_uq >> (64 - 8 * bv)) : 0;
}});
0x30: zap({{
}});
}
- 0x13: decode INTFUNC { // integer multiplies
- 0x00: mull({{ Rc.sl = Ra.sl * Rb_or_imm.sl; }}, IntMultOp);
+ 0x13: decode INTFUNC { // integer multiplies
+ 0x00: mull({{ Rc_sl = Ra_sl * Rb_or_imm_sl; }}, IntMultOp);
0x20: mulq({{ Rc = Ra * Rb_or_imm; }}, IntMultOp);
0x30: umulh({{
uint64_t hi, lo;
}}, IntMultOp);
0x40: mullv({{
// 32-bit multiply with trap on overflow
- int64_t Rax = Ra.sl; // sign extended version of Ra.sl
- int64_t Rbx = Rb_or_imm.sl;
+ int64_t Rax = Ra_sl; // sign extended version of Ra_sl
+ int64_t Rbx = Rb_or_imm_sl;
int64_t tmp = Rax * Rbx;
// To avoid overflow, all the upper 32 bits must match
// the sign bit of the lower 32. We code this as
// checking the upper 33 bits for all 0s or all 1s.
uint64_t sign_bits = tmp<63:31>;
if (sign_bits != 0 && sign_bits != mask(33))
- fault = new IntegerOverflowFault;
- Rc.sl = tmp<31:0>;
+ fault = std::make_shared<IntegerOverflowFault>();
+ Rc_sl = tmp<31:0>;
}}, IntMultOp);
0x60: mulqv({{
// 64-bit multiply with trap on overflow
// the lower 64
if (!((hi == 0 && lo<63:> == 0) ||
(hi == mask(64) && lo<63:> == 1)))
- fault = new IntegerOverflowFault;
+ fault = std::make_shared<IntegerOverflowFault>();
Rc = lo;
}}, IntMultOp);
}
0x1c: decode INTFUNC {
- 0x00: decode RA { 31: sextb({{ Rc.sb = Rb_or_imm< 7:0>; }}); }
- 0x01: decode RA { 31: sextw({{ Rc.sw = Rb_or_imm<15:0>; }}); }
+ 0x00: decode RA { 31: sextb({{ Rc_sb = Rb_or_imm< 7:0>; }}); }
+ 0x01: decode RA { 31: sextw({{ Rc_sw = Rb_or_imm<15:0>; }}); }
+
+ 0x30: ctpop({{
+ uint64_t count = 0;
+ for (int i = 0; Rb<63:i>; ++i) {
+ if (Rb<i:i> == 0x1)
+ ++count;
+ }
+ Rc = count;
+ }}, IntAluOp);
+
+ 0x31: perr({{
+ uint64_t temp = 0;
+ int hi = 7;
+ int lo = 0;
+ for (int i = 0; i < 8; ++i) {
+ uint8_t ra_ub = Ra_uq<hi:lo>;
+ uint8_t rb_ub = Rb_uq<hi:lo>;
+ temp += (ra_ub >= rb_ub) ?
+ (ra_ub - rb_ub) : (rb_ub - ra_ub);
+ hi += 8;
+ lo += 8;
+ }
+ Rc = temp;
+ }});
+
0x32: ctlz({{
uint64_t count = 0;
uint64_t temp = Rb;
if (!(temp<7:0>)) { temp >>= 8; count += 8; }
if (!(temp<3:0>)) { temp >>= 4; count += 4; }
if (!(temp<1:0>)) { temp >>= 2; count += 2; }
+ if (!(temp<0:0> & ULL(0x1))) {
+ temp >>= 1; count += 1;
+ }
if (!(temp<0:0> & ULL(0x1))) count += 1;
Rc = count;
}}, IntAluOp);
- format FailUnimpl {
- 0x30: ctpop();
- 0x31: perr();
- 0x34: unpkbw();
- 0x35: unpkbl();
- 0x36: pkwb();
- 0x37: pklb();
- 0x38: minsb8();
- 0x39: minsw4();
- 0x3a: minub8();
- 0x3b: minuw4();
- 0x3c: maxub8();
- 0x3d: maxuw4();
- 0x3e: maxsb8();
- 0x3f: maxsw4();
- }
+
+ 0x34: unpkbw({{
+ Rc = (Rb_uq<7:0>
+ | (Rb_uq<15:8> << 16)
+ | (Rb_uq<23:16> << 32)
+ | (Rb_uq<31:24> << 48));
+ }}, IntAluOp);
+
+ 0x35: unpkbl({{
+ Rc = (Rb_uq<7:0> | (Rb_uq<15:8> << 32));
+ }}, IntAluOp);
+
+ 0x36: pkwb({{
+ Rc = (Rb_uq<7:0>
+ | (Rb_uq<23:16> << 8)
+ | (Rb_uq<39:32> << 16)
+ | (Rb_uq<55:48> << 24));
+ }}, IntAluOp);
+
+ 0x37: pklb({{
+ Rc = (Rb_uq<7:0> | (Rb_uq<39:32> << 8));
+ }}, IntAluOp);
+
+ 0x38: minsb8({{
+ uint64_t temp = 0;
+ int hi = 63;
+ int lo = 56;
+ for (int i = 7; i >= 0; --i) {
+ int8_t ra_sb = Ra_uq<hi:lo>;
+ int8_t rb_sb = Rb_uq<hi:lo>;
+ temp = ((temp << 8)
+ | ((ra_sb < rb_sb) ? Ra_uq<hi:lo>
+ : Rb_uq<hi:lo>));
+ hi -= 8;
+ lo -= 8;
+ }
+ Rc = temp;
+ }});
+
+ 0x39: minsw4({{
+ uint64_t temp = 0;
+ int hi = 63;
+ int lo = 48;
+ for (int i = 3; i >= 0; --i) {
+ int16_t ra_sw = Ra_uq<hi:lo>;
+ int16_t rb_sw = Rb_uq<hi:lo>;
+ temp = ((temp << 16)
+ | ((ra_sw < rb_sw) ? Ra_uq<hi:lo>
+ : Rb_uq<hi:lo>));
+ hi -= 16;
+ lo -= 16;
+ }
+ Rc = temp;
+ }});
+
+ 0x3a: minub8({{
+ uint64_t temp = 0;
+ int hi = 63;
+ int lo = 56;
+ for (int i = 7; i >= 0; --i) {
+ uint8_t ra_ub = Ra_uq<hi:lo>;
+ uint8_t rb_ub = Rb_uq<hi:lo>;
+ temp = ((temp << 8)
+ | ((ra_ub < rb_ub) ? Ra_uq<hi:lo>
+ : Rb_uq<hi:lo>));
+ hi -= 8;
+ lo -= 8;
+ }
+ Rc = temp;
+ }});
+
+ 0x3b: minuw4({{
+ uint64_t temp = 0;
+ int hi = 63;
+ int lo = 48;
+ for (int i = 3; i >= 0; --i) {
+ uint16_t ra_sw = Ra_uq<hi:lo>;
+ uint16_t rb_sw = Rb_uq<hi:lo>;
+ temp = ((temp << 16)
+ | ((ra_sw < rb_sw) ? Ra_uq<hi:lo>
+ : Rb_uq<hi:lo>));
+ hi -= 16;
+ lo -= 16;
+ }
+ Rc = temp;
+ }});
+
+ 0x3c: maxub8({{
+ uint64_t temp = 0;
+ int hi = 63;
+ int lo = 56;
+ for (int i = 7; i >= 0; --i) {
+ uint8_t ra_ub = Ra_uq<hi:lo>;
+ uint8_t rb_ub = Rb_uq<hi:lo>;
+ temp = ((temp << 8)
+ | ((ra_ub > rb_ub) ? Ra_uq<hi:lo>
+ : Rb_uq<hi:lo>));
+ hi -= 8;
+ lo -= 8;
+ }
+ Rc = temp;
+ }});
+
+ 0x3d: maxuw4({{
+ uint64_t temp = 0;
+ int hi = 63;
+ int lo = 48;
+ for (int i = 3; i >= 0; --i) {
+ uint16_t ra_uw = Ra_uq<hi:lo>;
+ uint16_t rb_uw = Rb_uq<hi:lo>;
+ temp = ((temp << 16)
+ | ((ra_uw > rb_uw) ? Ra_uq<hi:lo>
+ : Rb_uq<hi:lo>));
+ hi -= 16;
+ lo -= 16;
+ }
+ Rc = temp;
+ }});
+
+ 0x3e: maxsb8({{
+ uint64_t temp = 0;
+ int hi = 63;
+ int lo = 56;
+ for (int i = 7; i >= 0; --i) {
+ int8_t ra_sb = Ra_uq<hi:lo>;
+ int8_t rb_sb = Rb_uq<hi:lo>;
+ temp = ((temp << 8)
+ | ((ra_sb > rb_sb) ? Ra_uq<hi:lo>
+ : Rb_uq<hi:lo>));
+ hi -= 8;
+ lo -= 8;
+ }
+ Rc = temp;
+ }});
+
+ 0x3f: maxsw4({{
+ uint64_t temp = 0;
+ int hi = 63;
+ int lo = 48;
+ for (int i = 3; i >= 0; --i) {
+ int16_t ra_sw = Ra_uq<hi:lo>;
+ int16_t rb_sw = Rb_uq<hi:lo>;
+ temp = ((temp << 16)
+ | ((ra_sw > rb_sw) ? Ra_uq<hi:lo>
+ : Rb_uq<hi:lo>));
+ hi -= 16;
+ lo -= 16;
+ }
+ Rc = temp;
+ }});
format BasicOperateWithNopCheck {
0x70: decode RB {
- 31: ftoit({{ Rc = Fa.uq; }}, FloatCvtOp);
+ 31: ftoit({{ Rc = Fa_uq; }}, FloatCvtOp);
}
0x78: decode RB {
- 31: ftois({{ Rc.sl = t_to_s(Fa.uq); }},
+ 31: ftois({{ Rc_sl = t_to_s(Fa_uq); }},
FloatCvtOp);
}
}
format CondBranch {
0x39: beq({{ cond = (Ra == 0); }});
0x3d: bne({{ cond = (Ra != 0); }});
- 0x3e: bge({{ cond = (Ra.sq >= 0); }});
- 0x3f: bgt({{ cond = (Ra.sq > 0); }});
- 0x3b: ble({{ cond = (Ra.sq <= 0); }});
- 0x3a: blt({{ cond = (Ra.sq < 0); }});
+ 0x3e: bge({{ cond = (Ra_sq >= 0); }});
+ 0x3f: bgt({{ cond = (Ra_sq > 0); }});
+ 0x3b: ble({{ cond = (Ra_sq <= 0); }});
+ 0x3a: blt({{ cond = (Ra_sq < 0); }});
0x38: blbc({{ cond = ((Ra & 1) == 0); }});
0x3c: blbs({{ cond = ((Ra & 1) == 1); }});
0x4: decode RB {
31: decode FP_FULLFUNC {
format BasicOperateWithNopCheck {
- 0x004: itofs({{ Fc.uq = s_to_t(Ra.ul); }}, FloatCvtOp);
- 0x024: itoft({{ Fc.uq = Ra.uq; }}, FloatCvtOp);
- 0x014: FailUnimpl::itoff(); // VAX-format conversion
+ 0x004: itofs({{ Fc_uq = s_to_t(Ra_ul); }}, FloatCvtOp);
+ 0x024: itoft({{ Fc_uq = Ra_uq; }}, FloatCvtOp);
+ 0x014: FailUnimpl::itoff(); // VAX-format conversion
}
}
}
#if SS_COMPATIBLE_FP
0x0b: sqrts({{
if (Fb < 0.0)
- fault = new ArithmeticFault;
+ fault = std::make_shared<ArithmeticFault>();
Fc = sqrt(Fb);
}}, FloatSqrtOp);
#else
0x0b: sqrts({{
- if (Fb.sf < 0.0)
- fault = new ArithmeticFault;
- Fc.sf = sqrt(Fb.sf);
+ if (Fb_sf < 0.0)
+ fault = std::make_shared<ArithmeticFault>();
+ Fc_sf = sqrt(Fb_sf);
}}, FloatSqrtOp);
#endif
0x2b: sqrtt({{
if (Fb < 0.0)
- fault = new ArithmeticFault;
+ fault = std::make_shared<ArithmeticFault>();
Fc = sqrt(Fb);
}}, FloatSqrtOp);
}
0x02: muls({{ Fc = Fa * Fb; }}, FloatMultOp);
0x03: divs({{ Fc = Fa / Fb; }}, FloatDivOp);
#else
- 0x00: adds({{ Fc.sf = Fa.sf + Fb.sf; }});
- 0x01: subs({{ Fc.sf = Fa.sf - Fb.sf; }});
- 0x02: muls({{ Fc.sf = Fa.sf * Fb.sf; }}, FloatMultOp);
- 0x03: divs({{ Fc.sf = Fa.sf / Fb.sf; }}, FloatDivOp);
+ 0x00: adds({{ Fc_sf = Fa_sf + Fb_sf; }});
+ 0x01: subs({{ Fc_sf = Fa_sf - Fb_sf; }});
+ 0x02: muls({{ Fc_sf = Fa_sf * Fb_sf; }}, FloatMultOp);
+ 0x03: divs({{ Fc_sf = Fa_sf / Fb_sf; }}, FloatDivOp);
#endif
0x20: addt({{ Fc = Fa + Fb; }});
0x2f: decode FP_ROUNDMODE {
format FPFixedRounding {
// "chopped" i.e. round toward zero
- 0: cvttq({{ Fc.sq = (int64_t)trunc(Fb); }},
+ 0: cvttq({{ Fc_sq = (int64_t)trunc(Fb); }},
Chopped);
// round to minus infinity
- 1: cvttq({{ Fc.sq = (int64_t)floor(Fb); }},
+ 1: cvttq({{ Fc_sq = (int64_t)floor(Fb); }},
MinusInfinity);
}
- default: cvttq({{ Fc.sq = (int64_t)nearbyint(Fb); }});
+ default: cvttq({{ Fc_sq = (int64_t)nearbyint(Fb); }});
}
// The cvtts opcode is overloaded to be cvtst if the trap
format BasicOperateWithNopCheck {
// trap on denorm version "cvtst/s" is
// simulated same as cvtst
- 0x2ac, 0x6ac: cvtst({{ Fc = Fb.sf; }});
+ 0x2ac, 0x6ac: cvtst({{ Fc = Fb_sf; }});
}
- default: cvtts({{ Fc.sf = Fb; }});
+ default: cvtts({{ Fc_sf = Fb; }});
}
// The trapping mode for integer-to-FP conversions
// allowed. The full set of rounding modes are
// supported though.
0x3c: decode FP_TRAPMODE {
- 0,7: cvtqs({{ Fc.sf = Fb.sq; }});
+ 0,7: cvtqs({{ Fc_sf = Fb_sq; }});
}
0x3e: decode FP_TRAPMODE {
- 0,7: cvtqt({{ Fc = Fb.sq; }});
+ 0,7: cvtqt({{ Fc = Fb_sq; }});
}
}
}
0x17: decode FP_FULLFUNC {
format BasicOperateWithNopCheck {
0x010: cvtlq({{
- Fc.sl = (Fb.uq<63:62> << 30) | Fb.uq<58:29>;
+ Fc_sl = (Fb_uq<63:62> << 30) | Fb_uq<58:29>;
}});
0x030: cvtql({{
- Fc.uq = (Fb.uq<31:30> << 62) | (Fb.uq<29:0> << 29);
+ Fc_uq = (Fb_uq<31:30> << 62) | (Fb_uq<29:0> << 29);
}});
// We treat the precise & imprecise trapping versions of
// To avoid overflow, all the upper 32 bits must match
// the sign bit of the lower 32. We code this as
// checking the upper 33 bits for all 0s or all 1s.
- uint64_t sign_bits = Fb.uq<63:31>;
+ uint64_t sign_bits = Fb_uq<63:31>;
if (sign_bits != 0 && sign_bits != mask(33))
- fault = new IntegerOverflowFault;
- Fc.uq = (Fb.uq<31:30> << 62) | (Fb.uq<29:0> << 29);
+ fault = std::make_shared<IntegerOverflowFault>();
+ Fc_uq = (Fb_uq<31:30> << 62) | (Fb_uq<29:0> << 29);
}});
0x020: cpys({{ // copy sign
- Fc.uq = (Fa.uq<63:> << 63) | Fb.uq<62:0>;
+ Fc_uq = (Fa_uq<63:> << 63) | Fb_uq<62:0>;
}});
0x021: cpysn({{ // copy sign negated
- Fc.uq = (~Fa.uq<63:> << 63) | Fb.uq<62:0>;
+ Fc_uq = (~Fa_uq<63:> << 63) | Fb_uq<62:0>;
}});
0x022: cpyse({{ // copy sign and exponent
- Fc.uq = (Fa.uq<63:52> << 52) | Fb.uq<51:0>;
+ Fc_uq = (Fa_uq<63:52> << 52) | Fb_uq<51:0>;
}});
0x02a: fcmoveq({{ Fc = (Fa == 0) ? Fb : Fc; }});
0x02e: fcmovle({{ Fc = (Fa <= 0) ? Fb : Fc; }});
0x02f: fcmovgt({{ Fc = (Fa > 0) ? Fb : Fc; }});
- 0x024: mt_fpcr({{ FPCR = Fa.uq; }}, IsIprAccess);
- 0x025: mf_fpcr({{ Fa.uq = FPCR; }}, IsIprAccess);
+ 0x024: mt_fpcr({{ FPCR = Fa_uq; }}, IsIprAccess);
+ 0x025: mf_fpcr({{ Fa_uq = FPCR; }}, IsIprAccess);
}
}
format MiscPrefetch {
0xf800: wh64({{ EA = Rb & ~ULL(63); }},
- {{ xc->writeHint(EA, 64, memAccessFlags); }},
- mem_flags = NO_FAULT,
- inst_flags = [IsMemRef, IsDataPrefetch,
- IsStore, MemWriteOp]);
+ {{ ; }},
+ mem_flags = PREFETCH);
}
format BasicOperate {
0xc000: rpcc({{
-#if FULL_SYSTEM
- /* Rb is a fake dependency so here is a fun way to get
- * the parser to understand that.
- */
- Ra = xc->readMiscReg(AlphaISA::IPR_CC) + (Rb & 0);
-
-#else
- Ra = curTick;
-#endif
+ /* Rb is a fake dependency so here is a fun way to get
+ * the parser to understand that.
+ */
+ uint64_t unused_var M5_VAR_USED = Rb;
+ Ra = FullSystem ? xc->readMiscReg(IPR_CC) : curTick();
}}, IsUnverifiable);
// All of the barrier instructions below do nothing in
0x4400: wmb({{ }}, IsWriteBarrier, MemWriteOp);
}
-#if FULL_SYSTEM
- format BasicOperate {
- 0xe000: rc({{
+ 0xe000: decode FullSystemInt {
+ 0: FailUnimpl::rc_se();
+ default: BasicOperate::rc({{
Ra = IntrFlag;
IntrFlag = 0;
}}, IsNonSpeculative, IsUnverifiable);
- 0xf000: rs({{
+ }
+ 0xf000: decode FullSystemInt {
+ 0: FailUnimpl::rs_se();
+ default: BasicOperate::rs({{
Ra = IntrFlag;
IntrFlag = 1;
}}, IsNonSpeculative, IsUnverifiable);
}
-#else
- format FailUnimpl {
- 0xe000: rc();
- 0xf000: rs();
- }
-#endif
}
-#if FULL_SYSTEM
- 0x00: CallPal::call_pal({{
- if (!palValid ||
- (palPriv
- && xc->readMiscReg(AlphaISA::IPR_ICM) != AlphaISA::mode_kernel)) {
- // invalid pal function code, or attempt to do privileged
- // PAL call in non-kernel mode
- fault = new UnimplementedOpcodeFault;
- }
- else {
- // check to see if simulator wants to do something special
- // on this PAL call (including maybe suppress it)
- bool dopal = xc->simPalCheck(palFunc);
-
- if (dopal) {
- xc->setMiscReg(AlphaISA::IPR_EXC_ADDR, NPC);
- NPC = xc->readMiscReg(AlphaISA::IPR_PAL_BASE) + palOffset;
+ 0x00: decode FullSystemInt {
+ 0: decode PALFUNC {
+ format EmulatedCallPal {
+ 0x00: halt ({{
+ exitSimLoop("halt instruction encountered");
+ }}, IsNonSpeculative);
+ 0x83: callsys({{
+ xc->syscall(R0, &fault);
+ }}, IsSerializeAfter, IsNonSpeculative, IsSyscall);
+ // Read uniq reg into ABI return value register (r0)
+ 0x9e: rduniq({{ R0 = Runiq; }}, IsIprAccess);
+ // Write uniq reg with value from ABI arg register (r16)
+ 0x9f: wruniq({{ Runiq = R16; }}, IsIprAccess);
}
}
- }}, IsNonSpeculative);
-#else
- 0x00: decode PALFUNC {
- format EmulatedCallPal {
- 0x00: halt ({{
- exitSimLoop("halt instruction encountered");
- }}, IsNonSpeculative);
- 0x83: callsys({{
- xc->syscall(R0);
- }}, IsSerializeAfter, IsNonSpeculative);
- // Read uniq reg into ABI return value register (r0)
- 0x9e: rduniq({{ R0 = Runiq; }}, IsIprAccess);
- // Write uniq reg with value from ABI arg register (r16)
- 0x9f: wruniq({{ Runiq = R16; }}, IsIprAccess);
- }
+ default: CallPal::call_pal({{
+ if (!palValid ||
+ (palPriv
+ && xc->readMiscReg(IPR_ICM) != mode_kernel)) {
+ // invalid pal function code, or attempt to do privileged
+ // PAL call in non-kernel mode
+ fault = std::make_shared<UnimplementedOpcodeFault>();
+ } else {
+ // check to see if simulator wants to do something special
+ // on this PAL call (including maybe suppress it)
+ bool dopal = xc->simPalCheck(palFunc);
+
+ if (dopal) {
+ xc->setMiscReg(IPR_EXC_ADDR, NPC);
+ NPC = xc->readMiscReg(IPR_PAL_BASE) + palOffset;
+ }
+ }
+ }}, IsNonSpeculative);
}
-#endif
-#if FULL_SYSTEM
0x1b: decode PALMODE {
0: OpcdecFault::hw_st_quad();
1: decode HW_LDST_QUAD {
format HwLoad {
- 0: hw_ld({{ EA = (Rb + disp) & ~3; }}, {{ Ra = Mem.ul; }}, L);
- 1: hw_ld({{ EA = (Rb + disp) & ~7; }}, {{ Ra = Mem.uq; }}, Q);
+ 0: hw_ld({{ EA = (Rb + disp) & ~3; }}, {{ Ra = Mem_ul; }},
+ L, IsSerializing, IsSerializeBefore);
+ 1: hw_ld({{ EA = (Rb + disp) & ~7; }}, {{ Ra = Mem_uq; }},
+ Q, IsSerializing, IsSerializeBefore);
}
}
}
1: decode HW_LDST_COND {
0: decode HW_LDST_QUAD {
0: hw_st({{ EA = (Rb + disp) & ~3; }},
- {{ Mem.ul = Ra<31:0>; }}, L);
+ {{ Mem_ul = Ra<31:0>; }}, L, IsSerializing, IsSerializeBefore);
1: hw_st({{ EA = (Rb + disp) & ~7; }},
- {{ Mem.uq = Ra.uq; }}, Q);
+ {{ Mem_uq = Ra_uq; }}, Q, IsSerializing, IsSerializeBefore);
}
1: FailUnimpl::hw_st_cond();
IprToMiscRegIndex[ipr_index] : -1;
if(miscRegIndex < 0 || !IprIsReadable(miscRegIndex) ||
miscRegIndex >= NumInternalProcRegs)
- fault = new UnimplementedOpcodeFault;
+ fault = std::make_shared<UnimplementedOpcodeFault>();
else
Ra = xc->readMiscReg(miscRegIndex);
}}, IsIprAccess);
IprToMiscRegIndex[ipr_index] : -1;
if(miscRegIndex < 0 || !IprIsWritable(miscRegIndex) ||
miscRegIndex >= NumInternalProcRegs)
- fault = new UnimplementedOpcodeFault;
+ fault = std::make_shared<UnimplementedOpcodeFault>();
else
xc->setMiscReg(miscRegIndex, Ra);
if (traceData) { traceData->setData(Ra); }
}
}
- format BasicOperate {
- 0x1e: decode PALMODE {
- 0: OpcdecFault::hw_rei();
- 1:hw_rei({{ xc->hwrei(); }}, IsSerializing, IsSerializeBefore);
+ 0x1e: decode PALMODE {
+ 0: OpcdecFault::hw_rei();
+ format BasicOperate {
+ 1: hw_rei({{ xc->hwrei(); }}, IsSerializing, IsSerializeBefore);
}
+ }
+ format BasicOperate {
// M5 special opcodes use the reserved 0x01 opcode space
0x01: decode M5FUNC {
0x00: arm({{
PseudoInst::arm(xc->tcBase());
}}, IsNonSpeculative);
0x01: quiesce({{
- PseudoInst::quiesce(xc->tcBase());
+ // Don't sleep if (unmasked) interrupts are pending
+ Interrupts* interrupts =
+ xc->tcBase()->getCpuPtr()->getInterruptController(0);
+ if (interrupts->checkInterrupts(xc->tcBase())) {
+ PseudoInst::quiesceSkip(xc->tcBase());
+ } else {
+ PseudoInst::quiesce(xc->tcBase());
+ }
}}, IsNonSpeculative, IsQuiesce);
0x02: quiesceNs({{
PseudoInst::quiesceNs(xc->tcBase(), R16);
0x04: quiesceTime({{
R0 = PseudoInst::quiesceTime(xc->tcBase());
}}, IsNonSpeculative, IsUnverifiable);
- 0x10: ivlb({{
- warn_once("Obsolete M5 instruction ivlb encountered.\n");
+ 0x07: rpns({{
+ R0 = PseudoInst::rpns(xc->tcBase());
+ }}, IsNonSpeculative, IsUnverifiable);
+ 0x09: wakeCPU({{
+ PseudoInst::wakeCPU(xc->tcBase(), R16);
+ }}, IsNonSpeculative, IsUnverifiable);
+ 0x10: deprecated_ivlb({{
+ warn_once("Obsolete M5 ivlb instruction encountered.\n");
}});
- 0x11: ivle({{
- warn_once("Obsolete M5 instruction ivlb encountered.\n");
+ 0x11: deprecated_ivle({{
+ warn_once("Obsolete M5 ivlb instruction encountered.\n");
}});
- 0x20: m5exit_old({{
- PseudoInst::m5exit_old(xc->tcBase());
+ 0x20: deprecated_exit ({{
+ warn_once("deprecated M5 exit instruction encountered.\n");
+ PseudoInst::m5exit(xc->tcBase(), 0);
}}, No_OpClass, IsNonSpeculative);
0x21: m5exit({{
PseudoInst::m5exit(xc->tcBase(), R16);
0x31: loadsymbol({{
PseudoInst::loadsymbol(xc->tcBase());
}}, No_OpClass, IsNonSpeculative);
- 0x30: initparam({{ Ra = xc->tcBase()->getCpuPtr()->system->init_param; }});
+ 0x30: initparam({{
+ Ra = PseudoInst::initParam(xc->tcBase(), R16, R17);
+ }});
0x40: resetstats({{
PseudoInst::resetstats(xc->tcBase(), R16, R17);
}}, IsNonSpeculative);
PseudoInst::addsymbol(xc->tcBase(), R16, R17);
}}, IsNonSpeculative);
0x54: m5panic({{
- panic("M5 panic instruction called at pc=%#x.", xc->readPC());
+ panic("M5 panic instruction called at pc = %#x.", PC);
}}, IsNonSpeculative);
- 0x55: m5anBegin({{
- PseudoInst::anBegin(xc->tcBase(), R16);
+#define CPANN(lbl) CPA::cpa()->lbl(xc->tcBase())
+ 0x55: decode RA {
+ 0x00: m5a_old({{
+ panic("Deprecated M5 annotate instruction executed "
+ "at pc = %#x\n", PC);
+ }}, IsNonSpeculative);
+ 0x01: m5a_bsm({{
+ CPANN(swSmBegin);
+ }}, IsNonSpeculative);
+ 0x02: m5a_esm({{
+ CPANN(swSmEnd);
+ }}, IsNonSpeculative);
+ 0x03: m5a_begin({{
+ CPANN(swExplictBegin);
+ }}, IsNonSpeculative);
+ 0x04: m5a_end({{
+ CPANN(swEnd);
+ }}, IsNonSpeculative);
+ 0x06: m5a_q({{
+ CPANN(swQ);
+ }}, IsNonSpeculative);
+ 0x07: m5a_dq({{
+ CPANN(swDq);
+ }}, IsNonSpeculative);
+ 0x08: m5a_wf({{
+ CPANN(swWf);
+ }}, IsNonSpeculative);
+ 0x09: m5a_we({{
+ CPANN(swWe);
+ }}, IsNonSpeculative);
+ 0x0C: m5a_sq({{
+ CPANN(swSq);
+ }}, IsNonSpeculative);
+ 0x0D: m5a_aq({{
+ CPANN(swAq);
+ }}, IsNonSpeculative);
+ 0x0E: m5a_pq({{
+ CPANN(swPq);
+ }}, IsNonSpeculative);
+ 0x0F: m5a_l({{
+ CPANN(swLink);
+ }}, IsNonSpeculative);
+ 0x10: m5a_identify({{
+ CPANN(swIdentify);
+ }}, IsNonSpeculative);
+ 0x11: m5a_getid({{
+ R0 = CPANN(swGetId);
+ }}, IsNonSpeculative);
+ 0x13: m5a_scl({{
+ CPANN(swSyscallLink);
+ }}, IsNonSpeculative);
+ 0x14: m5a_rq({{
+ CPANN(swRq);
+ }}, IsNonSpeculative);
+ } // M5 Annotate Operations
+#undef CPANN
+ 0x56: m5reserved2({{
+ warn("M5 reserved opcode ignored");
}}, IsNonSpeculative);
- 0x56: m5anWait({{
- PseudoInst::anWait(xc->tcBase(), R16, R17);
+ 0x57: m5reserved3({{
+ warn("M5 reserved opcode ignored");
+ }}, IsNonSpeculative);
+ 0x58: m5reserved4({{
+ warn("M5 reserved opcode ignored");
+ }}, IsNonSpeculative);
+ 0x59: m5reserved5({{
+ warn("M5 reserved opcode ignored");
}}, IsNonSpeculative);
}
}
-#endif
}
projects / gem5.git / blobdiff