base: Delete alpha loader components.

[gem5.git] / src / arch / alpha / isa / fp.isa

diff --git a/src/arch/alpha/isa/fp.isa b/src/arch/alpha/isa/fp.isa
index 3b5575f6241f925ec7ad7f0ca70207f97d158d54..99d13acc54fa528b4612ac540fd48cea649699ea 100644 (file)
--- a/src/arch/alpha/isa/fp.isa
+++ b/src/arch/alpha/isa/fp.isa
@@ -32,9 +32,9 @@
 //
 // Floating-point instructions
 //
-//     Note that many FP-type instructions which do not support all the
-//     various rounding & trapping modes use the simpler format
-//     BasicOperateWithNopCheck.
+//      Note that many FP-type instructions which do not support all the
+//      various rounding & trapping modes use the simpler format
+//      BasicOperateWithNopCheck.
 //
 
 output exec {{
@@ -42,21 +42,17 @@ output exec {{
     /// instruction in full-system mode.
     /// @retval Full-system mode: NoFault if FP is enabled, FenFault
     /// if not.  Non-full-system mode: always returns NoFault.
-#if FULL_SYSTEM
-    inline Fault checkFpEnableFault(%(CPU_exec_context)s *xc)
+    inline Fault checkFpEnableFault(ExecContext *xc)
     {
-        Fault fault = NoFault; // dummy... this ipr access should not fault
-        if (!EV5::ICSR_FPE(xc->readMiscRegWithEffect(AlphaISA::IPR_ICSR))) {
-            fault = new FloatEnableFault;
+        Fault fault = NoFault;  // dummy... this ipr access should not fault
+        if (FullSystem && !ICSR_FPE(xc->readMiscReg(IPR_ICSR))) {
+            fault = std::make_shared<FloatEnableFault>();
         }
         return fault;
     }
-#else
-    inline Fault checkFpEnableFault(%(CPU_exec_context)s *xc)
-    {
-        return NoFault;
+    inline Fault checkVectorEnableFault(ExecContext *xc) {
+        return std::make_shared<VectorEnableFault>();
     }
-#endif
 }};
 
 output header {{
@@ -71,11 +67,11 @@ output header {{
       public:
         /// Alpha FP rounding modes.
         enum RoundingMode {
-            Chopped = 0,       ///< round toward zero
+            Chopped = 0,        ///< round toward zero
             Minus_Infinity = 1, ///< round toward minus infinity
-            Normal = 2,                ///< round to nearest (default)
-            Dynamic = 3,       ///< use FPCR setting (in instruction)
-            Plus_Infinity = 3  ///< round to plus inifinity (in FPCR)
+            Normal = 2,         ///< round to nearest (default)
+            Dynamic = 3,        ///< use FPCR setting (in instruction)
+            Plus_Infinity = 3   ///< round to plus inifinity (in FPCR)
         };
 
         /// Alpha FP trapping modes.
@@ -84,10 +80,10 @@ output header {{
         /// the assembly modifier is V rather than U.
         enum TrappingMode {
             /// default: nothing enabled
-            Imprecise = 0,                ///< no modifier
+            Imprecise = 0,                 ///< no modifier
             /// underflow/overflow traps enabled, inexact disabled
-            Underflow_Imprecise = 1,      ///< /U or /V
-            Underflow_Precise = 5,        ///< /SU or /SV
+            Underflow_Imprecise = 1,       ///< /U or /V
+            Underflow_Precise = 5,         ///< /SU or /SV
             /// underflow/overflow and inexact traps enabled
             Underflow_Inexact_Precise = 7  ///< /SUI or /SVI
         };
@@ -130,8 +126,8 @@ output header {{
 
         // This differs from the AlphaStaticInst version only in
         // printing suffixes for non-default rounding & trapping modes.
-        std::string
-        generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+        std::string generateDisassembly(
+                Addr pc, const SymbolTable *symtab) const override;
     };
 
 }};
@@ -154,9 +150,8 @@ output decoder {{
     {
         std::string mnem_str(mnemonic);
 
-#ifndef SS_COMPATIBLE_DISASSEMBLY
         std::string suffix("");
-        suffix += ((_destRegIdx[0] >= FP_Base_DepTag)
+        suffix += ((_destRegIdx[0].isFloatReg())
                    ? fpTrappingModeSuffix[trappingMode]
                    : intTrappingModeSuffix[trappingMode]);
         suffix += roundingModeSuffix[roundingMode];
@@ -164,7 +159,6 @@ output decoder {{
         if (suffix != "") {
             mnem_str = csprintf("%s/%s", mnemonic, suffix);
         }
-#endif
 
         std::stringstream ss;
         ccprintf(ss, "%-10s ", mnem_str.c_str());
@@ -192,10 +186,10 @@ output decoder {{
     }
 
     const int AlphaFP::alphaToC99RoundingMode[] = {
-        FE_TOWARDZERO, // Chopped
-        FE_DOWNWARD,   // Minus_Infinity
-        FE_TONEAREST,  // Normal
-        FE_UPWARD      // Dynamic in inst, Plus_Infinity in FPCR
+        M5_FE_TOWARDZERO,       // Chopped
+        M5_FE_DOWNWARD, // Minus_Infinity
+        M5_FE_TONEAREST,        // Normal
+        M5_FE_UPWARD    // Dynamic in inst, Plus_Infinity in FPCR
     };
 
     const char *AlphaFP::roundingModeSuffix[] = { "c", "m", "", "d" };
@@ -210,7 +204,7 @@ output decoder {{
 // FP instruction class execute method template.  Handles non-standard
 // rounding modes.
 def template FloatingPointExecute {{
-    Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
+    Fault %(class_name)s::execute(ExecContext *xc,
                                   Trace::InstRecord *traceData) const
     {
         if (trappingMode != Imprecise && !warnedOnTrapping) {
@@ -228,10 +222,10 @@ def template FloatingPointExecute {{
         if (roundingMode == Normal) {
             %(code)s;
         } else {
-            fesetround(getC99RoundingMode(
-                           xc->readMiscReg(AlphaISA::MISCREG_FPCR)));
+            m5_fesetround(getC99RoundingMode(
+                           xc->readMiscReg(MISCREG_FPCR)));
             %(code)s;
-            fesetround(FE_TONEAREST);
+            m5_fesetround(M5_FE_TONEAREST);
         }
 #else
         if (roundingMode != Normal && !warnedOnRounding) {
@@ -254,7 +248,7 @@ def template FloatingPointExecute {{
 // rounding mode control is needed.  Like BasicExecute, but includes
 // check & warning for non-standard trapping mode.
 def template FPFixedRoundingExecute {{
-    Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
+    Fault %(class_name)s::execute(ExecContext *xc,
                                   Trace::InstRecord *traceData) const
     {
         if (trappingMode != Imprecise && !warnedOnTrapping) {
@@ -293,7 +287,7 @@ def template FloatingPointDecode {{
 //   currently unimplemented (will fail).
 // - Generates NOP if FC == 31.
 def format FloatingPointOperate(code, *opt_args) {{
-    iop = InstObjParams(name, Name, 'AlphaFP', CodeBlock(code), opt_args)
+    iop = InstObjParams(name, Name, 'AlphaFP', code, opt_args)
     decode_block = FloatingPointDecode.subst(iop)
     header_output = BasicDeclare.subst(iop)
     decoder_output = BasicConstructor.subst(iop)
@@ -303,7 +297,7 @@ def format FloatingPointOperate(code, *opt_args) {{
 // Special format for cvttq where rounding mode is pre-decoded
 def format FPFixedRounding(code, class_suffix, *opt_args) {{
     Name += class_suffix
-    iop = InstObjParams(name, Name, 'AlphaFP', CodeBlock(code), opt_args)
+    iop = InstObjParams(name, Name, 'AlphaFP', code, opt_args)
     decode_block = FloatingPointDecode.subst(iop)
     header_output = BasicDeclare.subst(iop)
     decoder_output = BasicConstructor.subst(iop)