//
// Floating-point instructions
//
-// Note that many FP-type instructions which do not support all the
-// various rounding & trapping modes use the simpler format
-// BasicOperateWithNopCheck.
+// Note that many FP-type instructions which do not support all the
+// various rounding & trapping modes use the simpler format
+// BasicOperateWithNopCheck.
//
output exec {{
/// instruction in full-system mode.
/// @retval Full-system mode: NoFault if FP is enabled, FenFault
/// if not. Non-full-system mode: always returns NoFault.
-#if FULL_SYSTEM
- inline Fault checkFpEnableFault(%(CPU_exec_context)s *xc)
+ inline Fault checkFpEnableFault(ExecContext *xc)
{
- Fault fault = NoFault; // dummy... this ipr access should not fault
- if (!EV5::ICSR_FPE(xc->readMiscRegWithEffect(AlphaISA::IPR_ICSR))) {
- fault = new FloatEnableFault;
+ Fault fault = NoFault; // dummy... this ipr access should not fault
+ if (FullSystem && !ICSR_FPE(xc->readMiscReg(IPR_ICSR))) {
+ fault = std::make_shared<FloatEnableFault>();
}
return fault;
}
-#else
- inline Fault checkFpEnableFault(%(CPU_exec_context)s *xc)
- {
- return NoFault;
+ inline Fault checkVectorEnableFault(ExecContext *xc) {
+ return std::make_shared<VectorEnableFault>();
}
-#endif
}};
output header {{
public:
/// Alpha FP rounding modes.
enum RoundingMode {
- Chopped = 0, ///< round toward zero
+ Chopped = 0, ///< round toward zero
Minus_Infinity = 1, ///< round toward minus infinity
- Normal = 2, ///< round to nearest (default)
- Dynamic = 3, ///< use FPCR setting (in instruction)
- Plus_Infinity = 3 ///< round to plus inifinity (in FPCR)
+ Normal = 2, ///< round to nearest (default)
+ Dynamic = 3, ///< use FPCR setting (in instruction)
+ Plus_Infinity = 3 ///< round to plus inifinity (in FPCR)
};
/// Alpha FP trapping modes.
/// the assembly modifier is V rather than U.
enum TrappingMode {
/// default: nothing enabled
- Imprecise = 0, ///< no modifier
+ Imprecise = 0, ///< no modifier
/// underflow/overflow traps enabled, inexact disabled
- Underflow_Imprecise = 1, ///< /U or /V
- Underflow_Precise = 5, ///< /SU or /SV
+ Underflow_Imprecise = 1, ///< /U or /V
+ Underflow_Precise = 5, ///< /SU or /SV
/// underflow/overflow and inexact traps enabled
Underflow_Inexact_Precise = 7 ///< /SUI or /SVI
};
// This differs from the AlphaStaticInst version only in
// printing suffixes for non-default rounding & trapping modes.
- std::string
- generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+ std::string generateDisassembly(
+ Addr pc, const SymbolTable *symtab) const override;
};
}};
{
std::string mnem_str(mnemonic);
-#ifndef SS_COMPATIBLE_DISASSEMBLY
std::string suffix("");
- suffix += ((_destRegIdx[0] >= FP_Base_DepTag)
+ suffix += ((_destRegIdx[0].isFloatReg())
? fpTrappingModeSuffix[trappingMode]
: intTrappingModeSuffix[trappingMode]);
suffix += roundingModeSuffix[roundingMode];
if (suffix != "") {
mnem_str = csprintf("%s/%s", mnemonic, suffix);
}
-#endif
std::stringstream ss;
ccprintf(ss, "%-10s ", mnem_str.c_str());
}
const int AlphaFP::alphaToC99RoundingMode[] = {
- FE_TOWARDZERO, // Chopped
- FE_DOWNWARD, // Minus_Infinity
- FE_TONEAREST, // Normal
- FE_UPWARD // Dynamic in inst, Plus_Infinity in FPCR
+ M5_FE_TOWARDZERO, // Chopped
+ M5_FE_DOWNWARD, // Minus_Infinity
+ M5_FE_TONEAREST, // Normal
+ M5_FE_UPWARD // Dynamic in inst, Plus_Infinity in FPCR
};
const char *AlphaFP::roundingModeSuffix[] = { "c", "m", "", "d" };
// FP instruction class execute method template. Handles non-standard
// rounding modes.
def template FloatingPointExecute {{
- Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
+ Fault %(class_name)s::execute(ExecContext *xc,
Trace::InstRecord *traceData) const
{
if (trappingMode != Imprecise && !warnedOnTrapping) {
if (roundingMode == Normal) {
%(code)s;
} else {
- fesetround(getC99RoundingMode(
- xc->readMiscReg(AlphaISA::Fpcr_DepTag)));
+ m5_fesetround(getC99RoundingMode(
+ xc->readMiscReg(MISCREG_FPCR)));
%(code)s;
- fesetround(FE_TONEAREST);
+ m5_fesetround(M5_FE_TONEAREST);
}
#else
if (roundingMode != Normal && !warnedOnRounding) {
// rounding mode control is needed. Like BasicExecute, but includes
// check & warning for non-standard trapping mode.
def template FPFixedRoundingExecute {{
- Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
+ Fault %(class_name)s::execute(ExecContext *xc,
Trace::InstRecord *traceData) const
{
if (trappingMode != Imprecise && !warnedOnTrapping) {
// currently unimplemented (will fail).
// - Generates NOP if FC == 31.
def format FloatingPointOperate(code, *opt_args) {{
- iop = InstObjParams(name, Name, 'AlphaFP', CodeBlock(code), opt_args)
+ iop = InstObjParams(name, Name, 'AlphaFP', code, opt_args)
decode_block = FloatingPointDecode.subst(iop)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
// Special format for cvttq where rounding mode is pre-decoded
def format FPFixedRounding(code, class_suffix, *opt_args) {{
Name += class_suffix
- iop = InstObjParams(name, Name, 'AlphaFP', CodeBlock(code), opt_args)
+ iop = InstObjParams(name, Name, 'AlphaFP', code, opt_args)
decode_block = FloatingPointDecode.subst(iop)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)