ARM: Decode neon memory instructions.

[gem5.git] / src / arch / alpha / isa.cc

diff --git a/src/arch/alpha/isa.cc b/src/arch/alpha/isa.cc
index ed452cfc62a791968292dcce90bd85be86fc69bb..8b6da3649457a75ebc711be4980d10a282833302 100644 (file)
--- a/src/arch/alpha/isa.cc
+++ b/src/arch/alpha/isa.cc
@@ -29,51 +29,122 @@
  */
 
 #include "arch/alpha/isa.hh"
+#include "base/misc.hh"
 #include "cpu/thread_context.hh"
 
 namespace AlphaISA
 {
 
 void
-ISA::clear()
+ISA::serialize(EventManager *em, std::ostream &os)
 {
-    miscRegFile.clear();
+    SERIALIZE_SCALAR(fpcr);
+    SERIALIZE_SCALAR(uniq);
+    SERIALIZE_SCALAR(lock_flag);
+    SERIALIZE_SCALAR(lock_addr);
+    SERIALIZE_ARRAY(ipr, NumInternalProcRegs);
 }
 
-MiscReg
-ISA::readMiscRegNoEffect(int miscReg)
+void
+ISA::unserialize(EventManager *em, Checkpoint *cp, const std::string &section)
 {
-    return miscRegFile.readRegNoEffect((MiscRegIndex)miscReg);
+    UNSERIALIZE_SCALAR(fpcr);
+    UNSERIALIZE_SCALAR(uniq);
+    UNSERIALIZE_SCALAR(lock_flag);
+    UNSERIALIZE_SCALAR(lock_addr);
+    UNSERIALIZE_ARRAY(ipr, NumInternalProcRegs);
 }
 
-MiscReg
-ISA::readMiscReg(int miscReg, ThreadContext *tc)
-{
-    return miscRegFile.readReg((MiscRegIndex)miscReg, tc);
-}
 
-void
-ISA::setMiscRegNoEffect(int miscReg, const MiscReg val)
+MiscReg
+ISA::readMiscRegNoEffect(int misc_reg, ThreadID tid)
 {
-    miscRegFile.setRegNoEffect((MiscRegIndex)miscReg, val);
+    switch (misc_reg) {
+      case MISCREG_FPCR:
+        return fpcr;
+      case MISCREG_UNIQ:
+        return uniq;
+      case MISCREG_LOCKFLAG:
+        return lock_flag;
+      case MISCREG_LOCKADDR:
+        return lock_addr;
+      case MISCREG_INTR:
+        return intr_flag;
+      default:
+        assert(misc_reg < NumInternalProcRegs);
+        return ipr[misc_reg];
+    }
 }
 
-void
-ISA::setMiscReg(int miscReg, const MiscReg val, ThreadContext *tc)
+MiscReg
+ISA::readMiscReg(int misc_reg, ThreadContext *tc, ThreadID tid)
 {
-    miscRegFile.setReg((MiscRegIndex)miscReg, val, tc);
+    switch (misc_reg) {
+      case MISCREG_FPCR:
+        return fpcr;
+      case MISCREG_UNIQ:
+        return uniq;
+      case MISCREG_LOCKFLAG:
+        return lock_flag;
+      case MISCREG_LOCKADDR:
+        return lock_addr;
+      case MISCREG_INTR:
+        return intr_flag;
+      default:
+        return readIpr(misc_reg, tc);
+    }
 }
 
 void
-ISA::serialize(std::ostream &os)
+ISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid)
 {
-    miscRegFile.serialize(os);
+    switch (misc_reg) {
+      case MISCREG_FPCR:
+        fpcr = val;
+        return;
+      case MISCREG_UNIQ:
+        uniq = val;
+        return;
+      case MISCREG_LOCKFLAG:
+        lock_flag = val;
+        return;
+      case MISCREG_LOCKADDR:
+        lock_addr = val;
+        return;
+      case MISCREG_INTR:
+        intr_flag = val;
+        return;
+      default:
+        assert(misc_reg < NumInternalProcRegs);
+        ipr[misc_reg] = val;
+        return;
+    }
 }
 
 void
-ISA::unserialize(Checkpoint *cp, const std::string &section)
+ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc,
+                ThreadID tid)
 {
-    miscRegFile.unserialize(cp, section);
+    switch (misc_reg) {
+      case MISCREG_FPCR:
+        fpcr = val;
+        return;
+      case MISCREG_UNIQ:
+        uniq = val;
+        return;
+      case MISCREG_LOCKFLAG:
+        lock_flag = val;
+        return;
+      case MISCREG_LOCKADDR:
+        lock_addr = val;
+        return;
+      case MISCREG_INTR:
+        intr_flag = val;
+        return;
+      default:
+        setIpr(misc_reg, val, tc);
+        return;
+    }
 }
 
 }