alpha,arm,mips,power,riscv,sparc,x86,cpu: Get rid of ISA_HAS_DELAY_SLOT.

[gem5.git] / src / arch / alpha / isa_traits.hh

diff --git a/src/arch/alpha/isa_traits.hh b/src/arch/alpha/isa_traits.hh
index 663b144ab3d49717340c1414b00c1e9dcd4489c5..61688b5c8be155b3177db36e540c8bdfc6026850 100644 (file)
--- a/src/arch/alpha/isa_traits.hh
+++ b/src/arch/alpha/isa_traits.hh
@@ -34,82 +34,86 @@
 
 namespace LittleEndianGuest {}
 
+#include "arch/alpha/ipr.hh"
 #include "arch/alpha/types.hh"
-#include "arch/alpha/constants.hh"
-#include "arch/alpha/regfile.hh"
-#include "config/full_system.hh"
-#include "sim/host.hh"
-
-class StaticInstPtr;
-
-#if !FULL_SYSTEM
-class SyscallReturn {
-        public:
-           template <class T>
-           SyscallReturn(T v, bool s)
-           {
-               retval = (uint64_t)v;
-               success = s;
-           }
-
-           template <class T>
-           SyscallReturn(T v)
-           {
-               success = (v >= 0);
-               retval = (uint64_t)v;
-           }
-
-           ~SyscallReturn() {}
-
-           SyscallReturn& operator=(const SyscallReturn& s) {
-               retval = s.retval;
-               success = s.success;
-               return *this;
-           }
-
-           bool successful() { return success; }
-           uint64_t value() { return retval; }
-
-
-       private:
-           uint64_t retval;
-           bool success;
-};
+#include "base/types.hh"
+#include "cpu/static_inst_fwd.hh"
+
+namespace AlphaISA {
+
+using namespace LittleEndianGuest;
+
+StaticInstPtr decodeInst(ExtMachInst);
 
-#endif
+const Addr PageShift = 13;
+const Addr PageBytes = ULL(1) << PageShift;
+const Addr PageMask = ~(PageBytes - 1);
+const Addr PageOffset = PageBytes - 1;
 
-#if FULL_SYSTEM
-#include "arch/alpha/isa_fullsys_traits.hh"
-#endif
+////////////////////////////////////////////////////////////////////////
+//
+//  Translation stuff
+//
 
+const Addr PteShift = 3;
+const Addr NPtePageShift = PageShift - PteShift;
+const Addr NPtePage = ULL(1) << NPtePageShift;
+const Addr PteMask = NPtePage - 1;
 
-namespace AlphaISA
+// User Virtual
+const Addr USegBase = ULL(0x0);
+const Addr USegEnd = ULL(0x000003ffffffffff);
+
+// Kernel Direct Mapped
+const Addr K0SegBase = ULL(0xfffffc0000000000);
+const Addr K0SegEnd = ULL(0xfffffdffffffffff);
+
+// Kernel Virtual
+const Addr K1SegBase = ULL(0xfffffe0000000000);
+const Addr K1SegEnd = ULL(0xffffffffffffffff);
+
+////////////////////////////////////////////////////////////////////////
+//
+//  Interrupt levels
+//
+enum InterruptLevels
 {
+    INTLEVEL_SOFTWARE_MIN = 4,
+    INTLEVEL_SOFTWARE_MAX = 19,
 
-using namespace LittleEndianGuest;
+    INTLEVEL_EXTERNAL_MIN = 20,
+    INTLEVEL_EXTERNAL_MAX = 34,
 
-// redirected register map, really only used for the full system case.
-extern const int reg_redir[NumIntRegs];
-
-    StaticInstPtr decodeInst(ExtMachInst);
-
-#if !FULL_SYSTEM
-    static inline void setSyscallReturn(SyscallReturn return_value, RegFile *regs)
-    {
-        // check for error condition.  Alpha syscall convention is to
-        // indicate success/failure in reg a3 (r19) and put the
-        // return value itself in the standard return value reg (v0).
-        if (return_value.successful()) {
-            // no error
-            regs->setIntReg(SyscallSuccessReg, 0);
-            regs->setIntReg(ReturnValueReg, return_value.value());
-        } else {
-            // got an error, return details
-            regs->setIntReg(SyscallSuccessReg, (IntReg)-1);
-            regs->setIntReg(ReturnValueReg, -return_value.value());
-        }
-    }
-#endif
+    INTLEVEL_IRQ0 = 20,
+    INTLEVEL_IRQ1 = 21,
+    INTINDEX_ETHERNET = 0,
+    INTINDEX_SCSI = 1,
+    INTLEVEL_IRQ2 = 22,
+    INTLEVEL_IRQ3 = 23,
+
+    INTLEVEL_SERIAL = 33,
+
+    NumInterruptLevels = INTLEVEL_EXTERNAL_MAX
+};
+
+// EV5 modes
+enum mode_type
+{
+    mode_kernel = 0,        // kernel
+    mode_executive = 1,     // executive (unused by unix)
+    mode_supervisor = 2,    // supervisor (unused by unix)
+    mode_user = 3,          // user mode
+    mode_number             // number of modes
 };
 
+const int MachineBytes = 8;
+
+// Memory accesses cannot be unaligned
+const bool HasUnalignedMemAcc = false;
+
+const bool CurThreadInfoImplemented = true;
+const int CurThreadInfoReg = AlphaISA::IPR_PALtemp23;
+
+} // namespace AlphaISA
+
 #endif // __ARCH_ALPHA_ISA_TRAITS_HH__