alpha,arm,mips,power,riscv,sparc,x86,cpu: Get rid of ISA_HAS_DELAY_SLOT.

[gem5.git] / src / arch / alpha / isa_traits.hh

diff --git a/src/arch/alpha/isa_traits.hh b/src/arch/alpha/isa_traits.hh
index 66c240ef3a5c68a346f3ff3d763de49eebcdadbc..61688b5c8be155b3177db36e540c8bdfc6026850 100644 (file)
--- a/src/arch/alpha/isa_traits.hh
+++ b/src/arch/alpha/isa_traits.hh
@@ -34,11 +34,10 @@
 
 namespace LittleEndianGuest {}
 
+#include "arch/alpha/ipr.hh"
 #include "arch/alpha/types.hh"
 #include "base/types.hh"
-#include "config/full_system.hh"
-
-class StaticInstPtr;
+#include "cpu/static_inst_fwd.hh"
 
 namespace AlphaISA {
 
@@ -46,9 +45,6 @@ using namespace LittleEndianGuest;
 
 StaticInstPtr decodeInst(ExtMachInst);
 
-// Alpha Does NOT have a delay slot
-#define ISA_HAS_DELAY_SLOT 0
-
 const Addr PageShift = 13;
 const Addr PageBytes = ULL(1) << PageShift;
 const Addr PageMask = ~(PageBytes - 1);
@@ -76,9 +72,6 @@ const Addr K0SegEnd = ULL(0xfffffdffffffffff);
 const Addr K1SegBase = ULL(0xfffffe0000000000);
 const Addr K1SegEnd = ULL(0xffffffffffffffff);
 
-// For loading... XXX This maybe could be USegEnd?? --ali
-const Addr LoadAddrMask = ULL(0xffffffffff);
-
 ////////////////////////////////////////////////////////////////////////
 //
 //  Interrupt levels
@@ -113,23 +106,13 @@ enum mode_type
     mode_number             // number of modes
 };
 
-// Constants Related to the number of registers
+const int MachineBytes = 8;
 
-enum {
-    LogVMPageSize = 13,       // 8K bytes
-    VMPageSize = (1 << LogVMPageSize),
-
-    BranchPredAddrShiftAmt = 2, // instructions are 4-byte aligned
-
-    MachineBytes = 8,
-    WordBytes = 4,
-    HalfwordBytes = 2,
-    ByteBytes = 1,
-};
+// Memory accesses cannot be unaligned
+const bool HasUnalignedMemAcc = false;
 
-// return a no-op instruction... used for instruction fetch faults
-// Alpha UNOP (ldq_u r31,0(r0))
-const ExtMachInst NoopMachInst = 0x2ffe0000;
+const bool CurThreadInfoImplemented = true;
+const int CurThreadInfoReg = AlphaISA::IPR_PALtemp23;
 
 } // namespace AlphaISA