X86: Get rid of the unused getAllocator on the python base microop class.

[gem5.git] / src / arch / alpha / isa_traits.hh

diff --git a/src/arch/alpha/isa_traits.hh b/src/arch/alpha/isa_traits.hh
index f7114e5cc29ee17f4b85470091dd1e6046762791..a5a8bf5a080f171cc737a09a459e71d27f471a3d 100644 (file)
--- a/src/arch/alpha/isa_traits.hh
+++ b/src/arch/alpha/isa_traits.hh
@@ -34,8 +34,6 @@
 
 namespace LittleEndianGuest {}
 
-#include "arch/alpha/ipr.hh"
-#include "arch/alpha/max_inst_regs.hh"
 #include "arch/alpha/types.hh"
 #include "base/types.hh"
 #include "config/full_system.hh"
@@ -45,16 +43,6 @@ class StaticInstPtr;
 namespace AlphaISA {
 
 using namespace LittleEndianGuest;
-using AlphaISAInst::MaxInstSrcRegs;
-using AlphaISAInst::MaxInstDestRegs;
-
-// These enumerate all the registers for dependence tracking.
-enum DependenceTags {
-    // 0..31 are the integer regs 0..31
-    // 32..63 are the FP regs 0..31, i.e. use (reg + FP_Base_DepTag)
-    FP_Base_DepTag = 40,
-    Ctrl_Base_DepTag = 72
-};
 
 StaticInstPtr decodeInst(ExtMachInst);
 
@@ -127,50 +115,25 @@ enum mode_type
 
 // Constants Related to the number of registers
 
-const int NumIntArchRegs = 32;
-const int NumPALShadowRegs = 8;
-const int NumFloatArchRegs = 32;
-// @todo: Figure out what this number really should be.
-const int NumMiscArchRegs = 77;
-
-const int NumIntRegs = NumIntArchRegs + NumPALShadowRegs;
-const int NumFloatRegs = NumFloatArchRegs;
-const int NumMiscRegs = NumMiscArchRegs;
-
-const int TotalNumRegs =
-    NumIntRegs + NumFloatRegs + NumMiscRegs + NumInternalProcRegs;
-
-const int TotalDataRegs = NumIntRegs + NumFloatRegs;
-
-// semantically meaningful register indices
-const int ZeroReg = 31;     // architecturally meaningful
-// the rest of these depend on the ABI
-const int StackPointerReg = 30;
-const int GlobalPointerReg = 29;
-const int ProcedureValueReg = 27;
-const int ReturnAddressReg = 26;
-const int ReturnValueReg = 0;
-const int FramePointerReg = 15;
+enum {
+    LogVMPageSize = 13,       // 8K bytes
+    VMPageSize = (1 << LogVMPageSize),
 
-const int SyscallNumReg = 0;
-const int FirstArgumentReg = 16;
-const int SyscallPseudoReturnReg = 20;
-const int SyscallSuccessReg = 19;
+    BranchPredAddrShiftAmt = 2, // instructions are 4-byte aligned
 
-const int LogVMPageSize = 13;       // 8K bytes
-const int VMPageSize = (1 << LogVMPageSize);
-
-const int BranchPredAddrShiftAmt = 2; // instructions are 4-byte aligned
-
-const int MachineBytes = 8;
-const int WordBytes = 4;
-const int HalfwordBytes = 2;
-const int ByteBytes = 1;
+    MachineBytes = 8,
+    WordBytes = 4,
+    HalfwordBytes = 2,
+    ByteBytes = 1,
+};
 
 // return a no-op instruction... used for instruction fetch faults
 // Alpha UNOP (ldq_u r31,0(r0))
 const ExtMachInst NoopMachInst = 0x2ffe0000;
 
+// Memory accesses cannot be unaligned
+const bool HasUnalignedMemAcc = false;
+
 } // namespace AlphaISA
 
 #endif // __ARCH_ALPHA_ISA_TRAITS_HH__