ARM: Decode neon memory instructions.

[gem5.git] / src / arch / alpha / locked_mem.hh

diff --git a/src/arch/alpha/locked_mem.hh b/src/arch/alpha/locked_mem.hh
index 56b5ba5ed50c8c1b28da8630b36173bc53e6c5a6..86958e4c59e3162b4aa95787c8a6188952454a71 100644 (file)
--- a/src/arch/alpha/locked_mem.hh
+++ b/src/arch/alpha/locked_mem.hh
@@ -45,19 +45,18 @@
  * to do these manipulations based on the physical address.
  */
 
-#include "arch/alpha/miscregfile.hh"
+#include "arch/alpha/registers.hh"
 #include "base/misc.hh"
 #include "mem/request.hh"
 
+namespace AlphaISA {
 
-namespace AlphaISA
-{
 template <class XC>
 inline void
 handleLockedRead(XC *xc, Request *req)
 {
-    xc->setMiscReg(MISCREG_LOCKADDR, req->getPaddr() & ~0xf);
-    xc->setMiscReg(MISCREG_LOCKFLAG, true);
+    xc->setMiscRegNoEffect(MISCREG_LOCKADDR, req->getPaddr() & ~0xf);
+    xc->setMiscRegNoEffect(MISCREG_LOCKFLAG, true);
 }
 
 
@@ -71,13 +70,13 @@ handleLockedWrite(XC *xc, Request *req)
         req->setExtraData(2);
     } else {
         // standard store conditional
-        bool lock_flag = xc->readMiscReg(MISCREG_LOCKFLAG);
-        Addr lock_addr = xc->readMiscReg(MISCREG_LOCKADDR);
+        bool lock_flag = xc->readMiscRegNoEffect(MISCREG_LOCKFLAG);
+        Addr lock_addr = xc->readMiscRegNoEffect(MISCREG_LOCKADDR);
         if (!lock_flag || (req->getPaddr() & ~0xf) != lock_addr) {
             // Lock flag not set or addr mismatch in CPU;
             // don't even bother sending to memory system
             req->setExtraData(0);
-            xc->setMiscReg(MISCREG_LOCKFLAG, false);
+            xc->setMiscRegNoEffect(MISCREG_LOCKFLAG, false);
             // the rest of this code is not architectural;
             // it's just a debugging aid to help detect
             // livelock by warning on long sequences of failed
@@ -86,9 +85,9 @@ handleLockedWrite(XC *xc, Request *req)
             stCondFailures++;
             xc->setStCondFailures(stCondFailures);
             if (stCondFailures % 100000 == 0) {
-                warn("cpu %d: %d consecutive "
+                warn("context %d: %d consecutive "
                      "store conditional failures\n",
-                     xc->readCpuId(), stCondFailures);
+                     xc->contextId(), stCondFailures);
             }
 
             // store conditional failed already, so don't issue it to mem
@@ -99,7 +98,6 @@ handleLockedWrite(XC *xc, Request *req)
     return true;
 }
 
-
 } // namespace AlphaISA
 
-#endif
+#endif // __ARCH_ALPHA_LOCKED_MEM_HH__