X86: Get rid of the unused getAllocator on the python base microop class.

[gem5.git] / src / arch / alpha / tlb.cc

diff --git a/src/arch/alpha/tlb.cc b/src/arch/alpha/tlb.cc
index d20a0adc23c368587fa00305bb6125878b88b618..b578741d9316a2818973598454c0593b68381e32 100644 (file)
--- a/src/arch/alpha/tlb.cc
+++ b/src/arch/alpha/tlb.cc
@@ -39,7 +39,6 @@
 #include "base/inifile.hh"
 #include "base/str.hh"
 #include "base/trace.hh"
-#include "config/alpha_tlaser.hh"
 #include "cpu/thread_context.hh"
 
 using namespace std;
@@ -215,12 +214,7 @@ TLB::checkCacheability(RequestPtr &req, bool itb)
      */
 
 
-#if ALPHA_TLASER
-    if (req->getPaddr() & PAddrUncachedBit39)
-#else
-    if (req->getPaddr() & PAddrUncachedBit43)
-#endif
-    {
+    if (req->getPaddr() & PAddrUncachedBit43) {
         // IPR memory space not implemented
         if (PAddrIprSpace(req->getPaddr())) {
             return new UnimpFault("IPR memory space not implemented!");
@@ -228,11 +222,9 @@ TLB::checkCacheability(RequestPtr &req, bool itb)
             // mark request as uncacheable
             req->setFlags(Request::UNCACHEABLE);
 
-#if !ALPHA_TLASER
             // Clear bits 42:35 of the physical address (10-2 in
             // Tsunami manual)
             req->setPaddr(req->getPaddr() & PAddrUncachedMask);
-#endif
         }
         // We shouldn't be able to read from an uncachable address in Alpha as
         // we don't have a ROM and we don't want to try to fetch from a device 
@@ -398,13 +390,7 @@ TLB::translateInst(RequestPtr req, ThreadContext *tc)
 
         // VA<42:41> == 2, VA<39:13> maps directly to PA<39:13> for EV5
         // VA<47:41> == 0x7e, VA<40:13> maps directly to PA<40:13> for EV6
-#if ALPHA_TLASER
-        if ((MCSR_SP(tc->readMiscRegNoEffect(IPR_MCSR)) & 2) &&
-            VAddrSpaceEV5(req->getVaddr()) == 2)
-#else
-        if (VAddrSpaceEV6(req->getVaddr()) == 0x7e)
-#endif
-        {
+        if (VAddrSpaceEV6(req->getVaddr()) == 0x7e) {
             // only valid in kernel mode
             if (ICM_CM(tc->readMiscRegNoEffect(IPR_ICM)) !=
                 mode_kernel) {
@@ -414,14 +400,11 @@ TLB::translateInst(RequestPtr req, ThreadContext *tc)
 
             req->setPaddr(req->getVaddr() & PAddrImplMask);
 
-#if !ALPHA_TLASER
             // sign extend the physical address properly
             if (req->getPaddr() & PAddrUncachedBit40)
                 req->setPaddr(req->getPaddr() | ULL(0xf0000000000));
             else
                 req->setPaddr(req->getPaddr() & ULL(0xffffffffff));
-#endif
-
         } else {
             // not a physical address: need to look up pte
             int asn = DTB_ASN_ASN(tc->readMiscRegNoEffect(IPR_DTB_ASN));
@@ -469,7 +452,7 @@ TLB::translateData(RequestPtr req, ThreadContext *tc, bool write)
      * Check for alignment faults
      */
     if (req->getVaddr() & (req->getSize() - 1)) {
-        DPRINTF(TLB, "Alignment Fault on %#x, size = %d", req->getVaddr(),
+        DPRINTF(TLB, "Alignment Fault on %#x, size = %d\n", req->getVaddr(),
                 req->getSize());
         uint64_t flags = write ? MM_STAT_WR_MASK : 0;
         return new DtbAlignmentFault(req->getVaddr(), req->getFlags(), flags);
@@ -495,13 +478,7 @@ TLB::translateData(RequestPtr req, ThreadContext *tc, bool write)
         }
 
         // Check for "superpage" mapping
-#if ALPHA_TLASER
-        if ((MCSR_SP(tc->readMiscRegNoEffect(IPR_MCSR)) & 2) &&
-            VAddrSpaceEV5(req->getVaddr()) == 2)
-#else
-        if (VAddrSpaceEV6(req->getVaddr()) == 0x7e)
-#endif
-        {
+        if (VAddrSpaceEV6(req->getVaddr()) == 0x7e) {
             // only valid in kernel mode
             if (DTB_CM_CM(tc->readMiscRegNoEffect(IPR_DTB_CM)) !=
                 mode_kernel) {
@@ -515,14 +492,11 @@ TLB::translateData(RequestPtr req, ThreadContext *tc, bool write)
 
             req->setPaddr(req->getVaddr() & PAddrImplMask);
 
-#if !ALPHA_TLASER
             // sign extend the physical address properly
             if (req->getPaddr() & PAddrUncachedBit40)
                 req->setPaddr(req->getPaddr() | ULL(0xf0000000000));
             else
                 req->setPaddr(req->getPaddr() & ULL(0xffffffffff));
-#endif
-
         } else {
             if (write)
                 write_accesses++;
@@ -607,23 +581,20 @@ TLB::index(bool advance)
 }
 
 Fault
-TLB::translateAtomic(RequestPtr req, ThreadContext *tc,
-        bool write, bool execute)
+TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode)
 {
-    if (execute)
+    if (mode == Execute)
         return translateInst(req, tc);
     else
-        return translateData(req, tc, write);
+        return translateData(req, tc, mode == Write);
 }
 
 void
 TLB::translateTiming(RequestPtr req, ThreadContext *tc,
-        Translation *translation,
-        bool write, bool execute)
+        Translation *translation, Mode mode)
 {
     assert(translation);
-    translation->finish(translateAtomic(req, tc, write, execute),
-            req, tc, write, execute);
+    translation->finish(translateAtomic(req, tc, mode), req, tc, mode);
 }
 
 /* end namespace AlphaISA */ }