X86: Get rid of the unused getAllocator on the python base microop class.

[gem5.git] / src / arch / alpha / tlb.hh

diff --git a/src/arch/alpha/tlb.hh b/src/arch/alpha/tlb.hh
index f6256020e16e3e919c19f1016aaa44b9bac5778f..b84c2645144102123e4955f96956dab9dfbde715 100644 (file)
--- a/src/arch/alpha/tlb.hh
+++ b/src/arch/alpha/tlb.hh
@@ -24,98 +24,128 @@
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Nathan Binkert
+ *          Steve Reinhardt
  */
 
-#ifndef __ALPHA_MEMORY_HH__
-#define __ALPHA_MEMORY_HH__
+#ifndef __ARCH_ALPHA_TLB_HH__
+#define __ARCH_ALPHA_TLB_HH__
 
 #include <map>
 
 #include "arch/alpha/ev5.hh"
 #include "arch/alpha/isa_traits.hh"
-#include "arch/alpha/faults.hh"
+#include "arch/alpha/pagetable.hh"
+#include "arch/alpha/utility.hh"
+#include "arch/alpha/vtophys.hh"
 #include "base/statistics.hh"
 #include "mem/request.hh"
-#include "sim/sim_object.hh"
+#include "params/AlphaTLB.hh"
+#include "sim/faults.hh"
+#include "sim/tlb.hh"
+
+class ThreadContext;
+
+namespace AlphaISA {
 
-class ExecContext;
+class TlbEntry;
 
-class AlphaTLB : public SimObject
+class TLB : public BaseTLB
 {
   protected:
+    mutable Stats::Scalar fetch_hits;
+    mutable Stats::Scalar fetch_misses;
+    mutable Stats::Scalar fetch_acv;
+    mutable Stats::Formula fetch_accesses;
+    mutable Stats::Scalar read_hits;
+    mutable Stats::Scalar read_misses;
+    mutable Stats::Scalar read_acv;
+    mutable Stats::Scalar read_accesses;
+    mutable Stats::Scalar write_hits;
+    mutable Stats::Scalar write_misses;
+    mutable Stats::Scalar write_acv;
+    mutable Stats::Scalar write_accesses;
+    Stats::Formula data_hits;
+    Stats::Formula data_misses;
+    Stats::Formula data_acv;
+    Stats::Formula data_accesses;
+
+
     typedef std::multimap<Addr, int> PageTable;
-    PageTable lookupTable;     // Quick lookup into page table
+    PageTable lookupTable;  // Quick lookup into page table
 
-    AlphaISA::PTE *table;      // the Page Table
-    int size;                  // TLB Size
-    int nlu;                   // not last used entry (for replacement)
+    TlbEntry *table;        // the Page Table
+    int size;               // TLB Size
+    int nlu;                // not last used entry (for replacement)
 
     void nextnlu() { if (++nlu >= size) nlu = 0; }
-    AlphaISA::PTE *lookup(Addr vpn, uint8_t asn) const;
+    TlbEntry *lookup(Addr vpn, uint8_t asn);
 
   public:
-    AlphaTLB(const std::string &name, int size);
-    virtual ~AlphaTLB();
+    typedef AlphaTLBParams Params;
+    TLB(const Params *p);
+    virtual ~TLB();
+
+    virtual void regStats();
 
     int getsize() const { return size; }
 
-    AlphaISA::PTE &index(bool advance = true);
-    void insert(Addr vaddr, AlphaISA::PTE &pte);
+    TlbEntry &index(bool advance = true);
+    void insert(Addr vaddr, TlbEntry &entry);
 
     void flushAll();
     void flushProcesses();
     void flushAddr(Addr addr, uint8_t asn);
 
+    void
+    demapPage(Addr vaddr, uint64_t asn)
+    {
+        assert(asn < (1 << 8));
+        flushAddr(vaddr, asn);
+    }
+
     // static helper functions... really EV5 VM traits
-    static bool validVirtualAddress(Addr vaddr) {
+    static bool
+    validVirtualAddress(Addr vaddr)
+    {
         // unimplemented bits must be all 0 or all 1
-        Addr unimplBits = vaddr & EV5::VAddrUnImplMask;
-        return (unimplBits == 0) || (unimplBits == EV5::VAddrUnImplMask);
+        Addr unimplBits = vaddr & VAddrUnImplMask;
+        return unimplBits == 0 || unimplBits == VAddrUnImplMask;
     }
 
-    static Fault checkCacheability(RequestPtr &req);
+    static Fault checkCacheability(RequestPtr &req, bool itb = false);
 
     // Checkpointing
     virtual void serialize(std::ostream &os);
     virtual void unserialize(Checkpoint *cp, const std::string &section);
-};
-
-class AlphaITB : public AlphaTLB
-{
-  protected:
-    mutable Stats::Scalar<> hits;
-    mutable Stats::Scalar<> misses;
-    mutable Stats::Scalar<> acv;
-    mutable Stats::Formula accesses;
 
-  public:
-    AlphaITB(const std::string &name, int size);
-    virtual void regStats();
+    // Most recently used page table entries
+    TlbEntry *EntryCache[3];
+    inline void
+    flushCache()
+    {
+        memset(EntryCache, 0, 3 * sizeof(TlbEntry*));
+    }
 
-    Fault translate(RequestPtr &req, ExecContext *xc) const;
-};
+    inline TlbEntry *
+    updateCache(TlbEntry *entry) {
+        EntryCache[2] = EntryCache[1];
+        EntryCache[1] = EntryCache[0];
+        EntryCache[0] = entry;
+        return entry;
+    }
 
-class AlphaDTB : public AlphaTLB
-{
   protected:
-    mutable Stats::Scalar<> read_hits;
-    mutable Stats::Scalar<> read_misses;
-    mutable Stats::Scalar<> read_acv;
-    mutable Stats::Scalar<> read_accesses;
-    mutable Stats::Scalar<> write_hits;
-    mutable Stats::Scalar<> write_misses;
-    mutable Stats::Scalar<> write_acv;
-    mutable Stats::Scalar<> write_accesses;
-    Stats::Formula hits;
-    Stats::Formula misses;
-    Stats::Formula acv;
-    Stats::Formula accesses;
+    Fault translateData(RequestPtr req, ThreadContext *tc, bool write);
+    Fault translateInst(RequestPtr req, ThreadContext *tc);
 
   public:
-    AlphaDTB(const std::string &name, int size);
-    virtual void regStats();
-
-    Fault translate(RequestPtr &req, ExecContext *xc, bool write) const;
+    Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode);
+    void translateTiming(RequestPtr req, ThreadContext *tc,
+                         Translation *translation, Mode mode);
 };
 
-#endif // __ALPHA_MEMORY_HH__
+} // namespace AlphaISA
+
+#endif // __ARCH_ALPHA_TLB_HH__