* Steve Reinhardt
*/
-#ifndef __ALPHA_MEMORY_HH__
-#define __ALPHA_MEMORY_HH__
+#ifndef __ARCH_ALPHA_TLB_HH__
+#define __ARCH_ALPHA_TLB_HH__
#include <map>
#include "arch/alpha/vtophys.hh"
#include "base/statistics.hh"
#include "mem/request.hh"
+#include "params/AlphaTLB.hh"
#include "sim/faults.hh"
-#include "sim/sim_object.hh"
+#include "sim/tlb.hh"
class ThreadContext;
-namespace AlphaISA
-{
- class PTE;
-
- class TLB : public SimObject
- {
- protected:
- typedef std::multimap<Addr, int> PageTable;
- PageTable lookupTable; // Quick lookup into page table
-
- PTE *table; // the Page Table
- int size; // TLB Size
- int nlu; // not last used entry (for replacement)
-
- void nextnlu() { if (++nlu >= size) nlu = 0; }
- PTE *lookup(Addr vpn, uint8_t asn) const;
-
- public:
- TLB(const std::string &name, int size);
- virtual ~TLB();
+namespace AlphaISA {
- int getsize() const { return size; }
+class TlbEntry;
- PTE &index(bool advance = true);
- void insert(Addr vaddr, PTE &pte);
-
- void flushAll();
- void flushProcesses();
- void flushAddr(Addr addr, uint8_t asn);
-
- // static helper functions... really EV5 VM traits
- static bool validVirtualAddress(Addr vaddr) {
- // unimplemented bits must be all 0 or all 1
- Addr unimplBits = vaddr & EV5::VAddrUnImplMask;
- return (unimplBits == 0) || (unimplBits == EV5::VAddrUnImplMask);
- }
-
- static Fault checkCacheability(RequestPtr &req);
-
- // Checkpointing
- virtual void serialize(std::ostream &os);
- virtual void unserialize(Checkpoint *cp, const std::string §ion);
- };
+class TLB : public BaseTLB
+{
+ protected:
+ mutable Stats::Scalar fetch_hits;
+ mutable Stats::Scalar fetch_misses;
+ mutable Stats::Scalar fetch_acv;
+ mutable Stats::Formula fetch_accesses;
+ mutable Stats::Scalar read_hits;
+ mutable Stats::Scalar read_misses;
+ mutable Stats::Scalar read_acv;
+ mutable Stats::Scalar read_accesses;
+ mutable Stats::Scalar write_hits;
+ mutable Stats::Scalar write_misses;
+ mutable Stats::Scalar write_acv;
+ mutable Stats::Scalar write_accesses;
+ Stats::Formula data_hits;
+ Stats::Formula data_misses;
+ Stats::Formula data_acv;
+ Stats::Formula data_accesses;
+
+
+ typedef std::multimap<Addr, int> PageTable;
+ PageTable lookupTable; // Quick lookup into page table
+
+ TlbEntry *table; // the Page Table
+ int size; // TLB Size
+ int nlu; // not last used entry (for replacement)
+
+ void nextnlu() { if (++nlu >= size) nlu = 0; }
+ TlbEntry *lookup(Addr vpn, uint8_t asn);
+
+ public:
+ typedef AlphaTLBParams Params;
+ TLB(const Params *p);
+ virtual ~TLB();
+
+ virtual void regStats();
+
+ int getsize() const { return size; }
+
+ TlbEntry &index(bool advance = true);
+ void insert(Addr vaddr, TlbEntry &entry);
+
+ void flushAll();
+ void flushProcesses();
+ void flushAddr(Addr addr, uint8_t asn);
+
+ void
+ demapPage(Addr vaddr, uint64_t asn)
+ {
+ assert(asn < (1 << 8));
+ flushAddr(vaddr, asn);
+ }
- class ITB : public TLB
+ // static helper functions... really EV5 VM traits
+ static bool
+ validVirtualAddress(Addr vaddr)
{
- protected:
- mutable Stats::Scalar<> hits;
- mutable Stats::Scalar<> misses;
- mutable Stats::Scalar<> acv;
- mutable Stats::Formula accesses;
+ // unimplemented bits must be all 0 or all 1
+ Addr unimplBits = vaddr & VAddrUnImplMask;
+ return unimplBits == 0 || unimplBits == VAddrUnImplMask;
+ }
- public:
- ITB(const std::string &name, int size);
- virtual void regStats();
+ static Fault checkCacheability(RequestPtr &req, bool itb = false);
- Fault translate(RequestPtr &req, ThreadContext *tc) const;
- };
+ // Checkpointing
+ virtual void serialize(std::ostream &os);
+ virtual void unserialize(Checkpoint *cp, const std::string §ion);
- class DTB : public TLB
+ // Most recently used page table entries
+ TlbEntry *EntryCache[3];
+ inline void
+ flushCache()
{
- protected:
- mutable Stats::Scalar<> read_hits;
- mutable Stats::Scalar<> read_misses;
- mutable Stats::Scalar<> read_acv;
- mutable Stats::Scalar<> read_accesses;
- mutable Stats::Scalar<> write_hits;
- mutable Stats::Scalar<> write_misses;
- mutable Stats::Scalar<> write_acv;
- mutable Stats::Scalar<> write_accesses;
- Stats::Formula hits;
- Stats::Formula misses;
- Stats::Formula acv;
- Stats::Formula accesses;
-
- public:
- DTB(const std::string &name, int size);
- virtual void regStats();
-
- Fault translate(RequestPtr &req, ThreadContext *tc, bool write) const;
- };
-}
-
-#endif // __ALPHA_MEMORY_HH__
+ memset(EntryCache, 0, 3 * sizeof(TlbEntry*));
+ }
+
+ inline TlbEntry *
+ updateCache(TlbEntry *entry) {
+ EntryCache[2] = EntryCache[1];
+ EntryCache[1] = EntryCache[0];
+ EntryCache[0] = entry;
+ return entry;
+ }
+
+ protected:
+ Fault translateData(RequestPtr req, ThreadContext *tc, bool write);
+ Fault translateInst(RequestPtr req, ThreadContext *tc);
+
+ public:
+ Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode);
+ void translateTiming(RequestPtr req, ThreadContext *tc,
+ Translation *translation, Mode mode);
+};
+
+} // namespace AlphaISA
+
+#endif // __ARCH_ALPHA_TLB_HH__
projects / gem5.git / blobdiff