ARM: Decode neon memory instructions.

[gem5.git] / src / arch / alpha / types.hh

diff --git a/src/arch/alpha/types.hh b/src/arch/alpha/types.hh
index 5859052e9656d615afdc7b388a629804e111bca3..0d285c3b23502e632454a2ef4fe9787b86c968dd 100644 (file)
--- a/src/arch/alpha/types.hh
+++ b/src/arch/alpha/types.hh
@@ -32,36 +32,27 @@
 #ifndef __ARCH_ALPHA_TYPES_HH__
 #define __ARCH_ALPHA_TYPES_HH__
 
-#include "sim/host.hh"
+#include "base/types.hh"
 
-namespace AlphaISA
-{
-
-    typedef uint32_t MachInst;
-    typedef uint64_t ExtMachInst;
-    typedef uint8_t  RegIndex;
-
-    typedef uint64_t IntReg;
+namespace AlphaISA {
 
-    // floating point register file entry type
-    typedef double FloatReg;
-    typedef uint64_t FloatRegBits;
+typedef uint32_t MachInst;
+typedef uint64_t ExtMachInst;
 
-    // control register file contents
-    typedef uint64_t MiscReg;
+typedef uint64_t LargestRead;
 
-    typedef union {
-        IntReg  intreg;
-        FloatReg   fpreg;
-        MiscReg ctrlreg;
-    } AnyReg;
+enum annotes
+{
+    ANNOTE_NONE = 0,
+    // An impossible number for instruction annotations
+    ITOUCH_ANNOTE = 0xffffffff,
+};
 
-    enum annotes {
-        ANNOTE_NONE = 0,
-        // An impossible number for instruction annotations
-        ITOUCH_ANNOTE = 0xffffffff,
-    };
+struct CoreSpecific
+{
+    int core_type;
+};
 
 } // namespace AlphaISA
 
-#endif
+#endif // __ARCH_ALPHA_TYPES_HH__