ARM: Decode neon memory instructions.

[gem5.git] / src / arch / alpha / utility.cc

diff --git a/src/arch/alpha/utility.cc b/src/arch/alpha/utility.cc
index 23abceb93724ba7c91f3a4c6a876b53102d0e373..0d865e5208df9b17b44d984c0d36286f3fba2a77 100644 (file)
--- a/src/arch/alpha/utility.cc
+++ b/src/arch/alpha/utility.cc
@@ -29,6 +29,7 @@
  *          Ali Saidi
  */
 
+#include "arch/alpha/ev5.hh"
 #include "arch/alpha/utility.hh"
 
 #if FULL_SYSTEM
@@ -36,17 +37,18 @@
 #include "mem/vport.hh"
 #endif
 
-namespace AlphaISA
-{
+namespace AlphaISA {
 
-uint64_t getArgument(ThreadContext *tc, int number, bool fp)
+uint64_t
+getArgument(ThreadContext *tc, int number, bool fp)
 {
 #if FULL_SYSTEM
+    const int NumArgumentRegs = 6;
     if (number < NumArgumentRegs) {
         if (fp)
-            return tc->readFloatRegBits(ArgumentReg[number]);
+            return tc->readFloatRegBits(16 + number);
         else
-            return tc->readIntReg(ArgumentReg[number]);
+            return tc->readIntReg(16 + number);
     } else {
         Addr sp = tc->readIntReg(StackPointerReg);
         VirtualPort *vp = tc->getVirtPort();
@@ -56,9 +58,43 @@ uint64_t getArgument(ThreadContext *tc, int number, bool fp)
     }
 #else
     panic("getArgument() is Full system only\n");
-    M5_DUMMY_RETURN
+    M5_DUMMY_RETURN;
 #endif
 }
 
+void
+copyRegs(ThreadContext *src, ThreadContext *dest)
+{
+    // First loop through the integer registers.
+    for (int i = 0; i < NumIntRegs; ++i)
+        dest->setIntReg(i, src->readIntReg(i));
+
+    // Then loop through the floating point registers.
+    for (int i = 0; i < NumFloatRegs; ++i)
+        dest->setFloatRegBits(i, src->readFloatRegBits(i));
+
+    // Copy misc. registers
+    copyMiscRegs(src, dest);
+
+    // Lastly copy PC/NPC
+    dest->setPC(src->readPC());
+    dest->setNextPC(src->readNextPC());
+}
+
+void
+copyMiscRegs(ThreadContext *src, ThreadContext *dest)
+{
+    dest->setMiscRegNoEffect(MISCREG_FPCR,
+        src->readMiscRegNoEffect(MISCREG_FPCR));
+    dest->setMiscRegNoEffect(MISCREG_UNIQ,
+        src->readMiscRegNoEffect(MISCREG_UNIQ));
+    dest->setMiscRegNoEffect(MISCREG_LOCKFLAG,
+        src->readMiscRegNoEffect(MISCREG_LOCKFLAG));
+    dest->setMiscRegNoEffect(MISCREG_LOCKADDR,
+        src->readMiscRegNoEffect(MISCREG_LOCKADDR));
+
+    copyIprs(src, dest);
+}
+
 } // namespace AlphaISA