arch: Get rid of the unused (and mostly undefined) zeroRegisters.

[gem5.git] / src / arch / alpha / utility.hh

diff --git a/src/arch/alpha/utility.hh b/src/arch/alpha/utility.hh
index 71ee4aceb3330c91e04f985936b54fcae920dd33..46af1217ee5e60de2807df716d9f88f7c4074ee4 100644 (file)
--- a/src/arch/alpha/utility.hh
+++ b/src/arch/alpha/utility.hh
@@ -32,95 +32,36 @@
 #ifndef __ARCH_ALPHA_UTILITY_HH__
 #define __ARCH_ALPHA_UTILITY_HH__
 
-#include "arch/alpha/types.hh"
 #include "arch/alpha/isa_traits.hh"
-#include "arch/alpha/miscregfile.hh"
-#include "base/misc.hh"
-#include "config/full_system.hh"
+#include "arch/alpha/registers.hh"
+#include "arch/alpha/types.hh"
+#include "base/logging.hh"
+#include "cpu/static_inst.hh"
 #include "cpu/thread_context.hh"
+#include "arch/alpha/ev5.hh"
 
 namespace AlphaISA {
 
-uint64_t getArgument(ThreadContext *tc, int number, bool fp);
-
-inline bool
-inUserMode(ThreadContext *tc)
-{
-    return (tc->readMiscRegNoEffect(IPR_DTB_CM) & 0x18) != 0;
-}
-
-inline bool
-isCallerSaveIntegerRegister(unsigned int reg)
-{
-    panic("register classification not implemented");
-    return (reg >= 1 && reg <= 8) || (reg >= 22 && reg <= 25) || reg == 27;
-}
-
-inline bool
-isCalleeSaveIntegerRegister(unsigned int reg)
+inline PCState
+buildRetPC(const PCState &curPC, const PCState &callPC)
 {
-    panic("register classification not implemented");
-    return reg >= 9 && reg <= 15;
+    PCState retPC = callPC;
+    retPC.advance();
+    return retPC;
 }
 
-inline bool
-isCallerSaveFloatRegister(unsigned int reg)
-{
-    panic("register classification not implemented");
-    return false;
-}
+uint64_t getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp);
 
 inline bool
-isCalleeSaveFloatRegister(unsigned int reg)
-{
-    panic("register classification not implemented");
-    return false;
-}
-
-inline Addr
-alignAddress(const Addr &addr, unsigned int nbytes)
-{
-    return (addr & ~(nbytes - 1));
-}
-
-// Instruction address compression hooks
-inline Addr
-realPCToFetchPC(const Addr &addr)
-{
-    return addr;
-}
-
-inline Addr
-fetchPCToRealPC(const Addr &addr)
-{
-    return addr;
-}
-
-// the size of "fetched" instructions (not necessarily the size
-// of real instructions for PISA)
-inline size_t
-fetchInstSize()
-{
-    return sizeof(MachInst);
-}
-
-inline MachInst
-makeRegisterCopy(int dest, int src)
+inUserMode(ThreadContext *tc)
 {
-    panic("makeRegisterCopy not implemented");
-    return 0;
+    return (tc->readMiscRegNoEffect(IPR_DTB_CM) & 0x18) != 0;
 }
 
-/**
- * Function to insure ISA semantics about 0 registers.
- * @param tc The thread context.
- */
-template <class TC>
-void zeroRegisters(TC *tc);
-
 // Alpha IPR register accessors
 inline bool PcPAL(Addr addr) { return addr & 0x3; }
-inline void startupCPU(ThreadContext *tc, int cpuId) { tc->activate(0); }
+inline void startupCPU(ThreadContext *tc, int cpuId)
+{ tc->activate(); }
 
 ////////////////////////////////////////////////////////////////////////
 //
@@ -130,7 +71,7 @@ inline void startupCPU(ThreadContext *tc, int cpuId) { tc->activate(0); }
 inline Addr PteAddr(Addr a) { return (a & PteMask) << PteShift; }
 
 // User Virtual
-inline bool IsUSeg(Addr a) { return USegBase <= a && a <= USegEnd; }
+inline bool IsUSeg(Addr a) { assert(USegBase == 0); return a <= USegEnd; }
 
 // Kernel Direct Mapped
 inline bool IsK0Seg(Addr a) { return K0SegBase <= a && a <= K0SegEnd; }
@@ -148,16 +89,25 @@ RoundPage(Addr addr)
 { return (addr + PageBytes - 1) & ~(PageBytes - 1); }
 
 void initIPRs(ThreadContext *tc, int cpuId);
-#if FULL_SYSTEM
 void initCPU(ThreadContext *tc, int cpuId);
 
-/**
- * Function to check for and process any interrupts.
- * @param tc The thread context.
- */
-template <class TC>
-void processInterrupts(TC *tc);
-#endif
+void copyRegs(ThreadContext *src, ThreadContext *dest);
+
+void copyMiscRegs(ThreadContext *src, ThreadContext *dest);
+
+void skipFunction(ThreadContext *tc);
+
+inline void
+advancePC(PCState &pc, const StaticInstPtr &inst)
+{
+    pc.advance();
+}
+
+inline uint64_t
+getExecutingAsid(ThreadContext *tc)
+{
+    return DTB_ASN_ASN(tc->readMiscRegNoEffect(IPR_DTB_ASN));
+}
 
 } // namespace AlphaISA