arch: Get rid of the unused (and mostly undefined) zeroRegisters.

[gem5.git] / src / arch / alpha / utility.hh

diff --git a/src/arch/alpha/utility.hh b/src/arch/alpha/utility.hh
index 8759b49ce19adfbdc0c85c64c278fb618b1397af..46af1217ee5e60de2807df716d9f88f7c4074ee4 100644 (file)
--- a/src/arch/alpha/utility.hh
+++ b/src/arch/alpha/utility.hh
@@ -35,10 +35,10 @@
 #include "arch/alpha/isa_traits.hh"
 #include "arch/alpha/registers.hh"
 #include "arch/alpha/types.hh"
-#include "base/misc.hh"
-#include "config/full_system.hh"
+#include "base/logging.hh"
 #include "cpu/static_inst.hh"
 #include "cpu/thread_context.hh"
+#include "arch/alpha/ev5.hh"
 
 namespace AlphaISA {
 
@@ -58,16 +58,10 @@ inUserMode(ThreadContext *tc)
     return (tc->readMiscRegNoEffect(IPR_DTB_CM) & 0x18) != 0;
 }
 
-/**
- * Function to insure ISA semantics about 0 registers.
- * @param tc The thread context.
- */
-template <class TC>
-void zeroRegisters(TC *tc);
-
 // Alpha IPR register accessors
 inline bool PcPAL(Addr addr) { return addr & 0x3; }
-inline void startupCPU(ThreadContext *tc, int cpuId) { tc->activate(0); }
+inline void startupCPU(ThreadContext *tc, int cpuId)
+{ tc->activate(); }
 
 ////////////////////////////////////////////////////////////////////////
 //
@@ -77,7 +71,7 @@ inline void startupCPU(ThreadContext *tc, int cpuId) { tc->activate(0); }
 inline Addr PteAddr(Addr a) { return (a & PteMask) << PteShift; }
 
 // User Virtual
-inline bool IsUSeg(Addr a) { return USegBase <= a && a <= USegEnd; }
+inline bool IsUSeg(Addr a) { assert(USegBase == 0); return a <= USegEnd; }
 
 // Kernel Direct Mapped
 inline bool IsK0Seg(Addr a) { return K0SegBase <= a && a <= K0SegEnd; }
@@ -95,9 +89,7 @@ RoundPage(Addr addr)
 { return (addr + PageBytes - 1) & ~(PageBytes - 1); }
 
 void initIPRs(ThreadContext *tc, int cpuId);
-#if FULL_SYSTEM
 void initCPU(ThreadContext *tc, int cpuId);
-#endif
 
 void copyRegs(ThreadContext *src, ThreadContext *dest);
 
@@ -106,11 +98,17 @@ void copyMiscRegs(ThreadContext *src, ThreadContext *dest);
 void skipFunction(ThreadContext *tc);
 
 inline void
-advancePC(PCState &pc, const StaticInstPtr inst)
+advancePC(PCState &pc, const StaticInstPtr &inst)
 {
     pc.advance();
 }
 
+inline uint64_t
+getExecutingAsid(ThreadContext *tc)
+{
+    return DTB_ASN_ASN(tc->readMiscRegNoEffect(IPR_DTB_ASN));
+}
+
 } // namespace AlphaISA
 
 #endif // __ARCH_ALPHA_UTILITY_HH__