arch: Get rid of the unused (and mostly undefined) zeroRegisters.

[gem5.git] / src / arch / alpha / utility.hh

diff --git a/src/arch/alpha/utility.hh b/src/arch/alpha/utility.hh
index a5212506694225a3530efbcc94bc8c4004a4dadb..46af1217ee5e60de2807df716d9f88f7c4074ee4 100644 (file)
--- a/src/arch/alpha/utility.hh
+++ b/src/arch/alpha/utility.hh
@@ -35,7 +35,7 @@
 #include "arch/alpha/isa_traits.hh"
 #include "arch/alpha/registers.hh"
 #include "arch/alpha/types.hh"
-#include "base/misc.hh"
+#include "base/logging.hh"
 #include "cpu/static_inst.hh"
 #include "cpu/thread_context.hh"
 #include "arch/alpha/ev5.hh"
@@ -58,13 +58,6 @@ inUserMode(ThreadContext *tc)
     return (tc->readMiscRegNoEffect(IPR_DTB_CM) & 0x18) != 0;
 }
 
-/**
- * Function to insure ISA semantics about 0 registers.
- * @param tc The thread context.
- */
-template <class TC>
-void zeroRegisters(TC *tc);
-
 // Alpha IPR register accessors
 inline bool PcPAL(Addr addr) { return addr & 0x3; }
 inline void startupCPU(ThreadContext *tc, int cpuId)
@@ -78,7 +71,7 @@ inline void startupCPU(ThreadContext *tc, int cpuId)
 inline Addr PteAddr(Addr a) { return (a & PteMask) << PteShift; }
 
 // User Virtual
-inline bool IsUSeg(Addr a) { return USegBase <= a && a <= USegEnd; }
+inline bool IsUSeg(Addr a) { assert(USegBase == 0); return a <= USegEnd; }
 
 // Kernel Direct Mapped
 inline bool IsK0Seg(Addr a) { return K0SegBase <= a && a <= K0SegEnd; }