arch: Get rid of the unused (and mostly undefined) zeroRegisters.

[gem5.git] / src / arch / alpha / utility.hh

diff --git a/src/arch/alpha/utility.hh b/src/arch/alpha/utility.hh
index a94742320644d66823095f60a1e681efd11d08c4..46af1217ee5e60de2807df716d9f88f7c4074ee4 100644 (file)
--- a/src/arch/alpha/utility.hh
+++ b/src/arch/alpha/utility.hh
@@ -32,128 +32,83 @@
 #ifndef __ARCH_ALPHA_UTILITY_HH__
 #define __ARCH_ALPHA_UTILITY_HH__
 
-#include "config/full_system.hh"
+#include "arch/alpha/isa_traits.hh"
+#include "arch/alpha/registers.hh"
 #include "arch/alpha/types.hh"
-#include "arch/alpha/constants.hh"
-#include "arch/alpha/regfile.hh"
-#include "base/misc.hh"
+#include "base/logging.hh"
+#include "cpu/static_inst.hh"
+#include "cpu/thread_context.hh"
+#include "arch/alpha/ev5.hh"
 
-namespace AlphaISA
+namespace AlphaISA {
+
+inline PCState
+buildRetPC(const PCState &curPC, const PCState &callPC)
 {
+    PCState retPC = callPC;
+    retPC.advance();
+    return retPC;
+}
+
+uint64_t getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp);
+
+inline bool
+inUserMode(ThreadContext *tc)
+{
+    return (tc->readMiscRegNoEffect(IPR_DTB_CM) & 0x18) != 0;
+}
+
+// Alpha IPR register accessors
+inline bool PcPAL(Addr addr) { return addr & 0x3; }
+inline void startupCPU(ThreadContext *tc, int cpuId)
+{ tc->activate(); }
+
+////////////////////////////////////////////////////////////////////////
+//
+//  Translation stuff
+//
+
+inline Addr PteAddr(Addr a) { return (a & PteMask) << PteShift; }
+
+// User Virtual
+inline bool IsUSeg(Addr a) { assert(USegBase == 0); return a <= USegEnd; }
+
+// Kernel Direct Mapped
+inline bool IsK0Seg(Addr a) { return K0SegBase <= a && a <= K0SegEnd; }
+inline Addr K0Seg2Phys(Addr addr) { return addr & ~K0SegBase; }
+
+// Kernel Virtual
+inline bool IsK1Seg(Addr a) { return K1SegBase <= a && a <= K1SegEnd; }
 
-    static inline ExtMachInst
-    makeExtMI(MachInst inst, const uint64_t &pc) {
-#if FULL_SYSTEM
-        ExtMachInst ext_inst = inst;
-        if (pc && 0x1)
-            return ext_inst|=(static_cast<ExtMachInst>(pc & 0x1) << 32);
-        else
-            return ext_inst;
-#else
-        return ExtMachInst(inst);
-#endif
-    }
-
-    inline bool isCallerSaveIntegerRegister(unsigned int reg) {
-        panic("register classification not implemented");
-        return (reg >= 1 && reg <= 8 || reg >= 22 && reg <= 25 || reg == 27);
-    }
-
-    inline bool isCalleeSaveIntegerRegister(unsigned int reg) {
-        panic("register classification not implemented");
-        return (reg >= 9 && reg <= 15);
-    }
-
-    inline bool isCallerSaveFloatRegister(unsigned int reg) {
-        panic("register classification not implemented");
-        return false;
-    }
-
-    inline bool isCalleeSaveFloatRegister(unsigned int reg) {
-        panic("register classification not implemented");
-        return false;
-    }
-
-    inline Addr alignAddress(const Addr &addr,
-                                         unsigned int nbytes) {
-        return (addr & ~(nbytes - 1));
-    }
-
-    // Instruction address compression hooks
-    inline Addr realPCToFetchPC(const Addr &addr) {
-        return addr;
-    }
-
-    inline Addr fetchPCToRealPC(const Addr &addr) {
-        return addr;
-    }
-
-    // the size of "fetched" instructions (not necessarily the size
-    // of real instructions for PISA)
-    inline size_t fetchInstSize() {
-        return sizeof(MachInst);
-    }
-
-    inline MachInst makeRegisterCopy(int dest, int src) {
-        panic("makeRegisterCopy not implemented");
-        return 0;
-    }
-
-    // Machine operations
-
-    void saveMachineReg(AnyReg &savereg, const RegFile &reg_file,
-                               int regnum);
-
-    void restoreMachineReg(RegFile &regs, const AnyReg &reg,
-                                  int regnum);
-
-    /**
-     * Function to insure ISA semantics about 0 registers.
-     * @param xc The execution context.
-     */
-    template <class XC>
-    void zeroRegisters(XC *xc);
-
-#if FULL_SYSTEM
-    // Alpha IPR register accessors
-    inline bool PcPAL(Addr addr) { return addr & 0x1; }
-
-    ////////////////////////////////////////////////////////////////////////
-    //
-    //  Translation stuff
-    //
-
-    inline Addr PteAddr(Addr a) { return (a & PteMask) << PteShift; }
-
-    // User Virtual
-    inline bool IsUSeg(Addr a) { return USegBase <= a && a <= USegEnd; }
-
-    // Kernel Direct Mapped
-    inline bool IsK0Seg(Addr a) { return K0SegBase <= a && a <= K0SegEnd; }
-    inline Addr K0Seg2Phys(Addr addr) { return addr & ~K0SegBase; }
-
-    // Kernel Virtual
-    inline bool IsK1Seg(Addr a) { return K1SegBase <= a && a <= K1SegEnd; }
-
-    inline Addr
-    TruncPage(Addr addr)
-    { return addr & ~(PageBytes - 1); }
-
-    inline Addr
-    RoundPage(Addr addr)
-    { return (addr + PageBytes - 1) & ~(PageBytes - 1); }
-
-    void initCPU(ExecContext *xc, int cpuId);
-    void initIPRs(ExecContext *xc, int cpuId);
-
-    /**
-     * Function to check for and process any interrupts.
-     * @param xc The execution context.
-     */
-    template <class XC>
-    void processInterrupts(XC *xc);
-#endif
+inline Addr
+TruncPage(Addr addr)
+{ return addr & ~(PageBytes - 1); }
+
+inline Addr
+RoundPage(Addr addr)
+{ return (addr + PageBytes - 1) & ~(PageBytes - 1); }
+
+void initIPRs(ThreadContext *tc, int cpuId);
+void initCPU(ThreadContext *tc, int cpuId);
+
+void copyRegs(ThreadContext *src, ThreadContext *dest);
+
+void copyMiscRegs(ThreadContext *src, ThreadContext *dest);
+
+void skipFunction(ThreadContext *tc);
+
+inline void
+advancePC(PCState &pc, const StaticInstPtr &inst)
+{
+    pc.advance();
+}
+
+inline uint64_t
+getExecutingAsid(ThreadContext *tc)
+{
+    return DTB_ASN_ASN(tc->readMiscRegNoEffect(IPR_DTB_ASN));
+}
 
 } // namespace AlphaISA
 
-#endif
+#endif // __ARCH_ALPHA_UTILITY_HH__