ARM: Decode neon memory instructions.

[gem5.git] / src / arch / alpha / vtophys.cc

diff --git a/src/arch/alpha/vtophys.cc b/src/arch/alpha/vtophys.cc
index 439af3bd7d4823994e52e59e91c47fdd489ed97c..4a043d8d1df47667ae38b25865381c44b98a2f52 100644 (file)
--- a/src/arch/alpha/vtophys.cc
+++ b/src/arch/alpha/vtophys.cc
@@ -40,27 +40,28 @@
 #include "mem/vport.hh"
 
 using namespace std;
-using namespace AlphaISA;
 
-AlphaISA::PageTableEntry
-AlphaISA::kernel_pte_lookup(FunctionalPort *mem, Addr ptbr, AlphaISA::VAddr vaddr)
+namespace AlphaISA {
+
+PageTableEntry
+kernel_pte_lookup(FunctionalPort *mem, Addr ptbr, VAddr vaddr)
 {
     Addr level1_pte = ptbr + vaddr.level1();
-    AlphaISA::PageTableEntry level1 = mem->read<uint64_t>(level1_pte);
+    PageTableEntry level1 = mem->read<uint64_t>(level1_pte);
     if (!level1.valid()) {
         DPRINTF(VtoPhys, "level 1 PTE not valid, va = %#\n", vaddr);
         return 0;
     }
 
     Addr level2_pte = level1.paddr() + vaddr.level2();
-    AlphaISA::PageTableEntry level2 = mem->read<uint64_t>(level2_pte);
+    PageTableEntry level2 = mem->read<uint64_t>(level2_pte);
     if (!level2.valid()) {
         DPRINTF(VtoPhys, "level 2 PTE not valid, va = %#x\n", vaddr);
         return 0;
     }
 
     Addr level3_pte = level2.paddr() + vaddr.level3();
-    AlphaISA::PageTableEntry level3 = mem->read<uint64_t>(level3_pte);
+    PageTableEntry level3 = mem->read<uint64_t>(level3_pte);
     if (!level3.valid()) {
         DPRINTF(VtoPhys, "level 3 PTE not valid, va = %#x\n", vaddr);
         return 0;
@@ -69,13 +70,13 @@ AlphaISA::kernel_pte_lookup(FunctionalPort *mem, Addr ptbr, AlphaISA::VAddr vadd
 }
 
 Addr
-AlphaISA::vtophys(Addr vaddr)
+vtophys(Addr vaddr)
 {
     Addr paddr = 0;
-    if (AlphaISA::IsUSeg(vaddr))
+    if (IsUSeg(vaddr))
         DPRINTF(VtoPhys, "vtophys: invalid vaddr %#x", vaddr);
-    else if (AlphaISA::IsK0Seg(vaddr))
-        paddr = AlphaISA::K0Seg2Phys(vaddr);
+    else if (IsK0Seg(vaddr))
+        paddr = K0Seg2Phys(vaddr);
     else
         panic("vtophys: ptbr is not set on virtual lookup");
 
@@ -85,22 +86,22 @@ AlphaISA::vtophys(Addr vaddr)
 }
 
 Addr
-AlphaISA::vtophys(ThreadContext *tc, Addr addr)
+vtophys(ThreadContext *tc, Addr addr)
 {
-    AlphaISA::VAddr vaddr = addr;
-    Addr ptbr = tc->readMiscRegNoEffect(AlphaISA::IPR_PALtemp20);
+    VAddr vaddr = addr;
+    Addr ptbr = tc->readMiscRegNoEffect(IPR_PALtemp20);
     Addr paddr = 0;
     //@todo Andrew couldn't remember why he commented some of this code
     //so I put it back in. Perhaps something to do with gdb debugging?
-    if (AlphaISA::PcPAL(vaddr) && (vaddr < AlphaISA::PalMax)) {
+    if (PcPAL(vaddr) && (vaddr < PalMax)) {
         paddr = vaddr & ~ULL(1);
     } else {
-        if (AlphaISA::IsK0Seg(vaddr)) {
-            paddr = AlphaISA::K0Seg2Phys(vaddr);
+        if (IsK0Seg(vaddr)) {
+            paddr = K0Seg2Phys(vaddr);
         } else if (!ptbr) {
             paddr = vaddr;
         } else {
-            AlphaISA::PageTableEntry pte =
+            PageTableEntry pte =
                 kernel_pte_lookup(tc->getPhysPort(), ptbr, vaddr);
             if (pte.valid())
                 paddr = pte.paddr() | vaddr.offset();
@@ -113,3 +114,4 @@ AlphaISA::vtophys(ThreadContext *tc, Addr addr)
     return paddr;
 }
 
+} // namespace AlphaISA