misc: Merge branch v20.1.0.3 hotfix into develop

[gem5.git] / src / arch / arm / ArmISA.py

diff --git a/src/arch/arm/ArmISA.py b/src/arch/arm/ArmISA.py
index 0725726895422aed7d2850ac4bb24981057c365c..59d3919d51c76be8ceef4177bd4ae89787836c96 100644 (file)
--- a/src/arch/arm/ArmISA.py
+++ b/src/arch/arm/ArmISA.py
@@ -36,6 +36,7 @@
 from m5.params import *
 from m5.proxy import *
 
+from m5.SimObject import SimObject
 from m5.objects.ArmPMU import ArmPMU
 from m5.objects.ArmSystem import SveVectorLength
 from m5.objects.BaseISA import BaseISA
@@ -71,6 +72,7 @@ class ArmISA(BaseISA):
     # SuperSec | Coherent TLB | Bcast Maint |
     # BP Maint | Cache Maint Set/way | Cache Maint MVA
     id_mmfr3 = Param.UInt32(0x02102211, "Memory Model Feature Register 3")
+    id_mmfr4 = Param.UInt32(0x00000000, "Memory Model Feature Register 4")
 
     # See section B4.1.84 of ARM ARM
     # All values are latest for ARMv7-A profile
@@ -79,7 +81,9 @@ class ArmISA(BaseISA):
     id_isar2 = Param.UInt32(0x21232141, "Instruction Set Attribute Register 2")
     id_isar3 = Param.UInt32(0x01112131, "Instruction Set Attribute Register 3")
     id_isar4 = Param.UInt32(0x10010142, "Instruction Set Attribute Register 4")
-    id_isar5 = Param.UInt32(0x10000000, "Instruction Set Attribute Register 5")
+    id_isar5 = Param.UInt32(0x11000000, "Instruction Set Attribute Register 5")
+    # !I8MM | !BF16 | SPECRES = 0 | !SB | !FHM | DP | JSCVT
+    id_isar6 = Param.UInt32(0x00000001, "Instruction Set Attribute Register 6")
 
     fpsid = Param.UInt32(0x410430a0, "Floating-point System ID Register")
 
@@ -97,10 +101,11 @@ class ArmISA(BaseISA):
     id_aa64dfr1_el1 = Param.UInt64(0x0000000000000000,
         "AArch64 Debug Feature Register 1")
 
-    # !TME | !Atomic | !CRC32 | !SHA2 | !SHA1 | !AES
-    id_aa64isar0_el1 = Param.UInt64(0x0000000000000000,
+    # !FHM | !TME | !Atomic | !CRC32 | !SHA2 | RDM | !SHA1 | !AES
+    id_aa64isar0_el1 = Param.UInt64(0x0000000010000000,
         "AArch64 Instruction Set Attribute Register 0")
 
+    # !I8MM | !BF16 | SPECRES = 0 | !SB |
     # GPI = 0x0 | GPA = 0x1 | API=0x0 | FCMA | JSCVT | APA=0x1
     id_aa64isar1_el1 = Param.UInt64(0x0000000001011010,
         "AArch64 Instruction Set Attribute Register 1")
@@ -111,7 +116,8 @@ class ArmISA(BaseISA):
     # PAN | HPDS | !VHE
     id_aa64mmfr1_el1 = Param.UInt64(0x0000000000101000,
         "AArch64 Memory Model Feature Register 1")
-    id_aa64mmfr2_el1 = Param.UInt64(0x0000000000000000,
+    # |VARANGE
+    id_aa64mmfr2_el1 = Param.UInt64(0x0000000000010000,
         "AArch64 Memory Model Feature Register 2")
 
     # Any access (read/write) to an unimplemented
@@ -124,3 +130,7 @@ class ArmISA(BaseISA):
     # allocated, instead of an ArmSystem
     sve_vl_se = Param.SveVectorLength(1,
         "SVE vector length in quadwords (128-bit), SE-mode only")
+
+    # Recurse into subnodes to generate DTB entries. This is mainly needed to
+    # generate the PMU entry.
+    generateDeviceTree = SimObject.recurseDeviceTree