mem-cache: Add multiple eviction stats

[gem5.git] / src / arch / arm / ArmSystem.py

diff --git a/src/arch/arm/ArmSystem.py b/src/arch/arm/ArmSystem.py
index 98ff9591884226e90ce2fba53964645c85a1f52a..0e642153b6b905869b89dadc84374459cd33a95e 100644 (file)
--- a/src/arch/arm/ArmSystem.py
+++ b/src/arch/arm/ArmSystem.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2009, 2012-2013, 2015-2018 ARM Limited
+# Copyright (c) 2009, 2012-2013, 2015-2019 ARM Limited
 # All rights reserved.
 #
 # The license below extends only to copyright in the software and shall
@@ -41,17 +41,18 @@ from m5.options import *
 from m5.SimObject import *
 from m5.util.fdthelper import *
 
-from System import System
-from ArmSemihosting import ArmSemihosting
+from m5.objects.System import System
+from m5.objects.ArmSemihosting import ArmSemihosting
 
 class ArmMachineType(Enum):
     map = {
-        'RealViewPBX' : 1901,
         'VExpress_EMM' : 2272,
         'VExpress_EMM64' : 2272,
         'DTOnly' : -1,
     }
 
+class SveVectorLength(UInt8): min = 1; max = 16
+
 class ArmSystem(System):
     type = 'ArmSystem'
     cxx_header = "arch/arm/system.hh"
@@ -80,13 +81,34 @@ class ArmSystem(System):
         "Supported physical address range in bits when using AArch64 (ARMv8)")
     have_large_asid_64 = Param.Bool(False,
         "True if ASID is 16 bits in AArch64 (ARMv8)")
+    have_sve = Param.Bool(True,
+        "True if SVE is implemented (ARMv8)")
+    sve_vl = Param.SveVectorLength(1,
+        "SVE vector length in quadwords (128-bit)")
+    have_lse = Param.Bool(True,
+        "True if LSE is implemented (ARMv8.1)")
+    have_pan = Param.Bool(True,
+        "True if Priviledge Access Never is implemented (ARMv8.1)")
 
     semihosting = Param.ArmSemihosting(NULL,
         "Enable support for the Arm semihosting by settings this parameter")
 
-    m5ops_base = Param.Addr(0,
-        "Base of the 64KiB PA range used for memory-mapped m5ops. Set to 0 "
-        "to disable.")
+    dtb_filename = Param.String("",
+        "File that contains the Device Tree Blob. Don't use DTB if empty.")
+
+    def generateDtb(self, outdir, filename):
+        """
+        Autogenerate DTB. Arguments are the folder where the DTB
+        will be stored, and the name of the DTB file.
+        """
+        state = FdtState(addr_cells=2, size_cells=2, cpu_cells=1)
+        rootNode = self.generateDeviceTree(state)
+
+        fdt = Fdt()
+        fdt.add_rootnode(rootNode)
+        dtb_filename = os.path.join(outdir, filename)
+        self.dtb_filename = fdt.writeDtbFile(dtb_filename)
+
 
     def generateDeviceTree(self, state):
         # Generate a device tree root node for the system by creating the root
@@ -128,30 +150,16 @@ class GenericArmSystem(ArmSystem):
         "Machine id from http://www.arm.linux.org.uk/developer/machines/")
     atags_addr = Param.Addr("Address where default atags structure should " \
                                 "be written")
-    dtb_filename = Param.String("",
-        "File that contains the Device Tree Blob. Don't use DTB if empty.")
     early_kernel_symbols = Param.Bool(False,
         "enable early kernel symbol tables before MMU")
-    enable_context_switch_stats_dump = Param.Bool(False, "enable stats/task info dumping at context switch boundaries")
+    enable_context_switch_stats_dump = Param.Bool(False,
+        "enable stats/task info dumping at context switch boundaries")
 
     panic_on_panic = Param.Bool(False, "Trigger a gem5 panic if the " \
                                     "guest kernel panics")
     panic_on_oops = Param.Bool(False, "Trigger a gem5 panic if the " \
                                    "guest kernel oopses")
 
-    def generateDtb(self, outdir, filename):
-        """
-        Autogenerate DTB. Arguments are the folder where the DTB
-        will be stored, and the name of the DTB file.
-        """
-        state = FdtState(addr_cells=2, size_cells=2, cpu_cells=1)
-        rootNode = self.generateDeviceTree(state)
-
-        fdt = Fdt()
-        fdt.add_rootnode(rootNode)
-        dtb_filename = os.path.join(outdir, filename)
-        self.dtb_filename = fdt.writeDtbFile(dtb_filename)
-
 class LinuxArmSystem(GenericArmSystem):
     type = 'LinuxArmSystem'
     cxx_header = "arch/arm/linux/system.hh"