arch-arm: Remove m5ops_base declaration from ArmSystem

[gem5.git] / src / arch / arm / ArmSystem.py

diff --git a/src/arch/arm/ArmSystem.py b/src/arch/arm/ArmSystem.py
index daf94a97e08c9d171cf75ad8bf3733014640e9c4..c4cc51fbf17569819964b744cb2b36a7ae32949d 100644 (file)
--- a/src/arch/arm/ArmSystem.py
+++ b/src/arch/arm/ArmSystem.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2009, 2012-2013, 2015-2019 ARM Limited
+# Copyright (c) 2009, 2012-2013, 2015-2020 ARM Limited
 # All rights reserved.
 #
 # The license below extends only to copyright in the software and shall
@@ -32,9 +32,6 @@
 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Ali Saidi
-#          Glenn Bergmans
 
 from m5.params import *
 from m5.options import *
@@ -44,24 +41,12 @@ from m5.util.fdthelper import *
 from m5.objects.System import System
 from m5.objects.ArmSemihosting import ArmSemihosting
 
-class ArmMachineType(Enum):
-    map = {
-        'RealViewPBX' : 1901,
-        'VExpress_EMM' : 2272,
-        'VExpress_EMM64' : 2272,
-        'DTOnly' : -1,
-    }
-
 class SveVectorLength(UInt8): min = 1; max = 16
 
 class ArmSystem(System):
     type = 'ArmSystem'
     cxx_header = "arch/arm/system.hh"
     multi_proc = Param.Bool(True, "Multiprocessor system?")
-    boot_loader = VectorParam.String([],
-        "File that contains the boot loader code. Zero or more files may be "
-        "specified. The first boot loader that matches the kernel's "
-        "architecture will be used.")
     gic_cpu_addr = Param.Addr(0, "Addres of the GIC CPU interface")
     flags_addr = Param.Addr(0, "Address of the flags register for MP booting")
     have_security = Param.Bool(False,
@@ -73,7 +58,7 @@ class ArmSystem(System):
     have_lpae = Param.Bool(True, "True if LPAE is implemented")
     reset_addr = Param.Addr(0x0,
         "Reset address (ARMv8)")
-    auto_reset_addr = Param.Bool(False,
+    auto_reset_addr = Param.Bool(True,
         "Determine reset address from kernel entry point if no boot loader")
     highest_el_is_64 = Param.Bool(False,
         "True if the register width of the highest implemented exception level "
@@ -86,15 +71,32 @@ class ArmSystem(System):
         "True if SVE is implemented (ARMv8)")
     sve_vl = Param.SveVectorLength(1,
         "SVE vector length in quadwords (128-bit)")
+    have_lse = Param.Bool(True,
+        "True if LSE is implemented (ARMv8.1)")
     have_pan = Param.Bool(True,
         "True if Priviledge Access Never is implemented (ARMv8.1)")
 
     semihosting = Param.ArmSemihosting(NULL,
         "Enable support for the Arm semihosting by settings this parameter")
 
-    m5ops_base = Param.Addr(0,
-        "Base of the 64KiB PA range used for memory-mapped m5ops. Set to 0 "
-        "to disable.")
+    # Set to true if simulation provides a PSCI implementation
+    # This flag will be checked when auto-generating
+    # a PSCI node. A client (e.g Linux) would then be able to
+    # know if it can use the PSCI APIs
+    _have_psci = False
+
+    def generateDtb(self, filename):
+        """
+        Autogenerate DTB. Arguments are the folder where the DTB
+        will be stored, and the name of the DTB file.
+        """
+        state = FdtState(addr_cells=2, size_cells=2, cpu_cells=1)
+        rootNode = self.generateDeviceTree(state)
+
+        fdt = Fdt()
+        fdt.add_rootnode(rootNode)
+        fdt.writeDtbFile(filename)
+
 
     def generateDeviceTree(self, state):
         # Generate a device tree root node for the system by creating the root
@@ -128,51 +130,3 @@ class ArmSystem(System):
                 root.append(node)
 
         return root
-
-class GenericArmSystem(ArmSystem):
-    type = 'GenericArmSystem'
-    cxx_header = "arch/arm/system.hh"
-    machine_type = Param.ArmMachineType('DTOnly',
-        "Machine id from http://www.arm.linux.org.uk/developer/machines/")
-    atags_addr = Param.Addr("Address where default atags structure should " \
-                                "be written")
-    dtb_filename = Param.String("",
-        "File that contains the Device Tree Blob. Don't use DTB if empty.")
-    early_kernel_symbols = Param.Bool(False,
-        "enable early kernel symbol tables before MMU")
-    enable_context_switch_stats_dump = Param.Bool(False, "enable stats/task info dumping at context switch boundaries")
-
-    panic_on_panic = Param.Bool(False, "Trigger a gem5 panic if the " \
-                                    "guest kernel panics")
-    panic_on_oops = Param.Bool(False, "Trigger a gem5 panic if the " \
-                                   "guest kernel oopses")
-
-    def generateDtb(self, outdir, filename):
-        """
-        Autogenerate DTB. Arguments are the folder where the DTB
-        will be stored, and the name of the DTB file.
-        """
-        state = FdtState(addr_cells=2, size_cells=2, cpu_cells=1)
-        rootNode = self.generateDeviceTree(state)
-
-        fdt = Fdt()
-        fdt.add_rootnode(rootNode)
-        dtb_filename = os.path.join(outdir, filename)
-        self.dtb_filename = fdt.writeDtbFile(dtb_filename)
-
-class LinuxArmSystem(GenericArmSystem):
-    type = 'LinuxArmSystem'
-    cxx_header = "arch/arm/linux/system.hh"
-
-    @cxxMethod
-    def dumpDmesg(self):
-        """Dump dmesg from the simulated kernel to standard out"""
-        pass
-
-    # Have Linux systems for ARM auto-calc their load_addr_mask for proper
-    # kernel relocation.
-    load_addr_mask = 0x0
-
-class FreebsdArmSystem(GenericArmSystem):
-    type = 'FreebsdArmSystem'
-    cxx_header = "arch/arm/freebsd/system.hh"