# -*- mode:python -*-
-# Copyright (c) 2009 ARM Limited
+# Copyright (c) 2009, 2013, 2015 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
from m5.proxy import *
from MemObject import MemObject
+# Basic stage 1 translation objects
class ArmTableWalker(MemObject):
type = 'ArmTableWalker'
cxx_class = 'ArmISA::TableWalker'
- port = Port("Port for TableWalker to do walk the translation with")
- sys = Param.System(Parent.any, "system object parameter")
- min_backoff = Param.Tick(0, "Minimum backoff delay after failed send")
- max_backoff = Param.Tick(100000, "Minimum backoff delay after failed send")
+ cxx_header = "arch/arm/table_walker.hh"
+ is_stage2 = Param.Bool(False, "Is this object for stage 2 translation?")
+ num_squash_per_cycle = Param.Unsigned(2,
+ "Number of outstanding walks that can be squashed per cycle")
+
+ # The port to the memory system. This port is ultimately belonging
+ # to the Stage2MMU, and shared by the two table walkers, but we
+ # access it through the ITB and DTB walked objects in the CPU for
+ # symmetry with the other ISAs.
+ port = MasterPort("Port used by the two table walkers")
+ sys = Param.System(Parent.any, "system object parameter")
class ArmTLB(SimObject):
type = 'ArmTLB'
cxx_class = 'ArmISA::TLB'
+ cxx_header = "arch/arm/tlb.hh"
size = Param.Int(64, "TLB size")
walker = Param.ArmTableWalker(ArmTableWalker(), "HW Table walker")
+ is_stage2 = Param.Bool(False, "Is this a stage 2 TLB?")
+
+# Stage 2 translation objects, only used when virtualisation is being used
+class ArmStage2TableWalker(ArmTableWalker):
+ is_stage2 = True
+
+class ArmStage2TLB(ArmTLB):
+ size = 32
+ walker = ArmStage2TableWalker()
+ is_stage2 = True
+
+class ArmStage2MMU(SimObject):
+ type = 'ArmStage2MMU'
+ cxx_class = 'ArmISA::Stage2MMU'
+ cxx_header = 'arch/arm/stage2_mmu.hh'
+ tlb = Param.ArmTLB("Stage 1 TLB")
+ stage2_tlb = Param.ArmTLB("Stage 2 TLB")
+
+ sys = Param.System(Parent.any, "system object parameter")
+
+class ArmStage2IMMU(ArmStage2MMU):
+ # We rely on the itb being a parameter of the CPU, and get the
+ # appropriate object that way
+ tlb = Parent.itb
+ stage2_tlb = ArmStage2TLB()
+
+class ArmStage2DMMU(ArmStage2MMU):
+ # We rely on the dtb being a parameter of the CPU, and get the
+ # appropriate object that way
+ tlb = Parent.dtb
+ stage2_tlb = ArmStage2TLB()