MEM: Introduce the master/slave port roles in the Python classes

[gem5.git] / src / arch / arm / ArmTLB.py

diff --git a/src/arch/arm/ArmTLB.py b/src/arch/arm/ArmTLB.py
index fc6f51d84fd21946e159f7e737295ccb40a61496..8599fa75f57a8b81335a7c36a91832b6d8102ff5 100644 (file)
--- a/src/arch/arm/ArmTLB.py
+++ b/src/arch/arm/ArmTLB.py
@@ -45,7 +45,7 @@ from MemObject import MemObject
 class ArmTableWalker(MemObject):
     type = 'ArmTableWalker'
     cxx_class = 'ArmISA::TableWalker'
-    port = Port("Port for TableWalker to do walk the translation with")
+    port = MasterPort("Port for TableWalker to do walk the translation with")
     sys = Param.System(Parent.any, "system object parameter")
     min_backoff = Param.Tick(0, "Minimum backoff delay after failed send")
     max_backoff = Param.Tick(100000, "Minimum backoff delay after failed send")