ARM: Fix compilation on ARM after Gabe's change.

[gem5.git] / src / arch / arm / SConscript

diff --git a/src/arch/arm/SConscript b/src/arch/arm/SConscript
index 171c047181fd986edc10a847a7d341a7d16373fe..08a3c7048968b99bde0ceb296b7f234cbbed642a 100644 (file)
--- a/src/arch/arm/SConscript
+++ b/src/arch/arm/SConscript
@@ -47,6 +47,7 @@ if env['TARGET_ISA'] == 'arm':
 # Workaround for bug in SCons version > 0.97d20071212
 # Scons bug id: 2006 M5 Bug id: 308 
     Dir('isa/formats')
+    Source('decoder.cc')
     Source('faults.cc')
     Source('insts/macromem.cc')
     Source('insts/mem.cc')
@@ -56,12 +57,12 @@ if env['TARGET_ISA'] == 'arm':
     Source('insts/vfp.cc')
     Source('interrupts.cc')
     Source('isa.cc')
+    Source('isa_traits.cc')
     Source('linux/linux.cc')
     Source('linux/process.cc')
     Source('linux/system.cc')
     Source('miscregs.cc')
     Source('nativetrace.cc')
-    Source('predecoder.cc')
     Source('process.cc')
     Source('remote_gdb.cc')
     Source('stacktrace.cc')
@@ -77,9 +78,9 @@ if env['TARGET_ISA'] == 'arm':
     SimObject('ArmTLB.py')
 
     DebugFlag('Arm')
-    DebugFlag('TLBVerbose')
+    DebugFlag('Decoder', "Instructions returned by the predecoder")
     DebugFlag('Faults', "Trace Exceptions, interrupts, svc/swi")
-    DebugFlag('Predecoder', "Instructions returned by the predecoder")
+    DebugFlag('TLBVerbose')
 
     # Add in files generated by the ISA description.
     isa_desc_files = env.ISADesc('isa/main.isa')