ARM: Move some predecoder stuff into a .cc file.

[gem5.git] / src / arch / arm / SConscript

diff --git a/src/arch/arm/SConscript b/src/arch/arm/SConscript
index dbd12e240ba32b3ab11b85dbf983590ec9b4024f..6b13b4b749e3335f99257a622cf3e3a7354d9519 100644 (file)
--- a/src/arch/arm/SConscript
+++ b/src/arch/arm/SConscript
@@ -1,5 +1,17 @@
 # -*- mode:python -*-
 
+# Copyright (c) 2009 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder.  You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
 # Copyright (c) 2007-2008 The Florida State University
 # All rights reserved.
 #
@@ -27,6 +39,7 @@
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #
 # Authors: Stephen Hines
+#          Ali Saidi
 
 Import('*')
 
@@ -35,17 +48,36 @@ if env['TARGET_ISA'] == 'arm':
 # Scons bug id: 2006 M5 Bug id: 308 
     Dir('isa/formats')
     Source('faults.cc')
-    Source('pagetable.cc')
-    Source('regfile/regfile.cc')
+    Source('insts/branch.cc')
+    Source('insts/macromem.cc')
+    Source('insts/mem.cc')
+    Source('insts/misc.cc')
+    Source('insts/pred_inst.cc')
+    Source('insts/static_inst.cc')
+    Source('insts/vfp.cc')
+    Source('isa.cc')
+    Source('miscregs.cc')
+    Source('predecoder.cc')
+    Source('nativetrace.cc')
     Source('tlb.cc')
     Source('vtophys.cc')
+    Source('utility.cc')
 
+    SimObject('ArmNativeTrace.py')
     SimObject('ArmTLB.py')
-    TraceFlag('Arm')
 
+    TraceFlag('Arm')
+    TraceFlag('TLBVerbose')
+    TraceFlag('Faults', "Trace Exceptions, interrupts, svc/swi")
+    TraceFlag('Predecoder', "Instructions returned by the predecoder")
     if env['FULL_SYSTEM']:
-        #Insert Full-System Files Here
-        pass
+        Source('interrupts.cc')
+        Source('stacktrace.cc')
+        Source('system.cc')
+        Source('table_walker.cc')
+        
+        SimObject('ArmInterrupts.py')
+        SimObject('ArmSystem.py')
     else:
         Source('process.cc')
         Source('linux/linux.cc')