misc: Merged release-staging-v19.0.0.0 into develop

[gem5.git] / src / arch / arm / SConscript

diff --git a/src/arch/arm/SConscript b/src/arch/arm/SConscript
index 8d13a9b2da3b663e3ffded7e60e9a4bbd5b6f13e..b4e9bba8e11e95184680d32e381f9c66ffd510b0 100644 (file)
--- a/src/arch/arm/SConscript
+++ b/src/arch/arm/SConscript
@@ -1,6 +1,6 @@
 # -*- mode:python -*-
 
-# Copyright (c) 2009 ARM Limited
+# Copyright (c) 2009, 2012-2013, 2017-2018 ARM Limited
 # All rights reserved.
 #
 # The license below extends only to copyright in the software and shall
@@ -37,55 +37,79 @@
 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Stephen Hines
-#          Ali Saidi
 
 Import('*')
 
 if env['TARGET_ISA'] == 'arm':
 # Workaround for bug in SCons version > 0.97d20071212
-# Scons bug id: 2006 M5 Bug id: 308 
+# Scons bug id: 2006 M5 Bug id: 308
     Dir('isa/formats')
     Source('decoder.cc')
     Source('faults.cc')
+    Source('insts/branch.cc')
+    Source('insts/branch64.cc')
+    Source('insts/data64.cc')
     Source('insts/macromem.cc')
     Source('insts/mem.cc')
+    Source('insts/mem64.cc')
     Source('insts/misc.cc')
+    Source('insts/misc64.cc')
     Source('insts/pred_inst.cc')
+    Source('insts/pseudo.cc')
     Source('insts/static_inst.cc')
+    Source('insts/sve.cc')
+    Source('insts/sve_mem.cc')
     Source('insts/vfp.cc')
+    Source('insts/fplib.cc')
+    Source('insts/crypto.cc')
     Source('interrupts.cc')
     Source('isa.cc')
+    Source('isa_device.cc')
     Source('linux/linux.cc')
     Source('linux/process.cc')
     Source('linux/system.cc')
+    Source('freebsd/freebsd.cc')
+    Source('freebsd/process.cc')
+    Source('freebsd/system.cc')
     Source('miscregs.cc')
     Source('nativetrace.cc')
+    Source('pauth_helpers.cc')
+    Source('pmu.cc')
     Source('process.cc')
+    Source('qarma.cc')
     Source('remote_gdb.cc')
+    Source('semihosting.cc')
     Source('stacktrace.cc')
     Source('system.cc')
     Source('table_walker.cc')
+    Source('stage2_mmu.cc')
+    Source('stage2_lookup.cc')
     Source('tlb.cc')
+    Source('tlbi_op.cc')
     Source('utility.cc')
     Source('vtophys.cc')
 
     SimObject('ArmInterrupts.py')
     SimObject('ArmISA.py')
     SimObject('ArmNativeTrace.py')
+    SimObject('ArmSemihosting.py')
     SimObject('ArmSystem.py')
     SimObject('ArmTLB.py')
+    SimObject('ArmPMU.py')
 
     DebugFlag('Arm')
+    DebugFlag('Semihosting')
     DebugFlag('Decoder', "Instructions returned by the predecoder")
     DebugFlag('Faults', "Trace Exceptions, interrupts, svc/swi")
+    DebugFlag('PMUVerbose', "Performance Monitor")
     DebugFlag('TLBVerbose')
 
-    # Add in files generated by the ISA description.
-    isa_desc_files = env.ISADesc('isa/main.isa')
-    # Only non-header files need to be compiled.
-    for f in isa_desc_files:
-        if not f.path.endswith('.hh'):
-            Source(f)
+    # Add files generated by the ISA description.
+    ISADesc('isa/main.isa', decoder_splits=3, exec_splits=6)
 
+    GdbXml('arm/arm-with-neon.xml', 'gdb_xml_arm_target')
+    GdbXml('arm/arm-core.xml', 'gdb_xml_arm_core')
+    GdbXml('arm/arm-vfpv3.xml', 'gdb_xml_arm_vfpv3')
+    GdbXml('aarch64.xml', 'gdb_xml_aarch64_target')
+    GdbXml('aarch64-core.xml', 'gdb_xml_aarch64_core')
+    GdbXml('aarch64-fpu.xml', 'gdb_xml_aarch64_fpu')