Mem: Reclaim some request flags used by MIPS for alignment checking.

[gem5.git] / src / arch / arm / SConscript

diff --git a/src/arch/arm/SConscript b/src/arch/arm/SConscript
index 73fcc730b9761425184063761e0c4db31e17c257..df84763b5360b09ae77ff4afd36b563a1e1d2df6 100644 (file)
--- a/src/arch/arm/SConscript
+++ b/src/arch/arm/SConscript
@@ -48,29 +48,33 @@ if env['TARGET_ISA'] == 'arm':
 # Scons bug id: 2006 M5 Bug id: 308 
     Dir('isa/formats')
     Source('faults.cc')
-    Source('insts/branch.cc')
     Source('insts/macromem.cc')
     Source('insts/mem.cc')
     Source('insts/misc.cc')
     Source('insts/pred_inst.cc')
     Source('insts/static_inst.cc')
     Source('insts/vfp.cc')
+    Source('isa.cc')
     Source('miscregs.cc')
+    Source('predecoder.cc')
     Source('nativetrace.cc')
     Source('tlb.cc')
-    Source('vtophys.cc')
     Source('utility.cc')
 
     SimObject('ArmNativeTrace.py')
     SimObject('ArmTLB.py')
 
     TraceFlag('Arm')
+    TraceFlag('TLBVerbose')
     TraceFlag('Faults', "Trace Exceptions, interrupts, svc/swi")
     TraceFlag('Predecoder', "Instructions returned by the predecoder")
     if env['FULL_SYSTEM']:
         Source('interrupts.cc')
         Source('stacktrace.cc')
         Source('system.cc')
+        Source('vtophys.cc')
+        Source('linux/system.cc')
+        Source('table_walker.cc')
         
         SimObject('ArmInterrupts.py')
         SimObject('ArmSystem.py')