fastmodel: add interface to update system counter freq

[gem5.git] / src / arch / arm / fastmodel / CortexA76 / x2 / x2.lisa

diff --git a/src/arch/arm/fastmodel/CortexA76/x2/x2.lisa b/src/arch/arm/fastmodel/CortexA76/x2/x2.lisa
index e0f7a933036ba4ec5a72fde9d6ba7d2ba4dcb9bd..0279140552deac1bea9eb2785dbf0dcae82a4555 100644 (file)
--- a/src/arch/arm/fastmodel/CortexA76/x2/x2.lisa
+++ b/src/arch/arm/fastmodel/CortexA76/x2/x2.lisa
@@ -35,7 +35,7 @@ component CortexA76x2
         // Clocks.
         clock1Hz : MasterClock();
         clockDiv : ClockDivider();
-        clockDivPeriph : ClockDivider(mul=0x01800000);
+        clockDivPeriph : ClockDivider();
     }
 
     connection
@@ -77,6 +77,13 @@ component CortexA76x2
             clockDiv.rate.set64(mul, div);
         }
     }
+    slave port<ExportedClockRateControl> periph_clock_rate_s
+    {
+        behavior set_mul_div(uint64_t mul, uint64_t div)
+        {
+            clockDivPeriph.rate.set64(mul, div);
+        }
+    }
     slave port<GICv3Comms> redistributor[2];
 
     // External ports for CPU-to-GIC signals