misc: BaseCPU using ArchMMU instead of ArchDTB/ArchITB

[gem5.git] / src / arch / arm / fastmodel / iris / thread_context.hh

diff --git a/src/arch/arm/fastmodel/iris/thread_context.hh b/src/arch/arm/fastmodel/iris/thread_context.hh
index 4175e93633a1271789b0f0b41044053095a83ca8..5e5d7838e198183e39c2350bdb581fe07bd632ce 100644 (file)
--- a/src/arch/arm/fastmodel/iris/thread_context.hh
+++ b/src/arch/arm/fastmodel/iris/thread_context.hh
@@ -23,8 +23,6 @@
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Gabe Black
  */
 
 #ifndef __ARCH_ARM_FASTMODEL_IRIS_THREAD_CONTEXT_HH__
@@ -59,13 +57,19 @@ class ThreadContext : public ::ThreadContext
     int _threadId;
     ContextID _contextId;
     System *_system;
-    ::BaseTLB *_dtb;
-    ::BaseTLB *_itb;
+    ::BaseMMU *_mmu;
+    ::BaseISA *_isa;
 
     std::string _irisPath;
-    iris::InstanceId _instId;
+    iris::InstanceId _instId = iris::IRIS_UINT64_MAX;
+
+    // Temporary holding places for the vector reg accessors to return.
+    // These are not updated live, only when requested.
+    mutable std::vector<ArmISA::VecRegContainer> vecRegs;
+    mutable std::vector<ArmISA::VecPredRegContainer> vecPredRegs;
 
-    Status _status;
+    Status _status = Active;
+    Event *enableAfterPseudoEvent;
 
     virtual void initFromIrisInstance(const ResourceMap &resources);
 
@@ -76,7 +80,16 @@ class ThreadContext : public ::ThreadContext
 
 
     ResourceIds miscRegIds;
-    ResourceIds intRegIds;
+    ResourceIds intReg32Ids;
+    ResourceIds intReg64Ids;
+    ResourceIds flattenedIntIds;
+    ResourceIds ccRegIds;
+
+    iris::ResourceId pcRscId = iris::IRIS_UINT64_MAX;
+    iris::ResourceId icountRscId;
+
+    ResourceIds vecRegIds;
+    ResourceIds vecPredRegIds;
 
     std::vector<iris::MemorySpaceInfo> memorySpaces;
     std::vector<iris::MemorySupportedAddressTranslationResult> translations;
@@ -97,14 +110,15 @@ class ThreadContext : public ::ThreadContext
     struct BpInfo
     {
         Addr pc;
-        BpId id;
-        std::list<PCEvent *> events;
+        std::vector<BpId> ids;
+        using EventList = std::list<PCEvent *>;
+        std::shared_ptr<EventList> events;
 
-        BpInfo(Addr _pc) : pc(_pc), id(iris::IRIS_UINT64_MAX) {}
+        BpInfo(Addr _pc) : pc(_pc), events(new EventList) {}
 
-        bool empty() const { return events.empty(); }
-        bool validId() const { return id != iris::IRIS_UINT64_MAX; }
-        void clearId() { id = iris::IRIS_UINT64_MAX; }
+        bool empty() const { return events->empty(); }
+        bool validIds() const { return !ids.empty(); }
+        void clearIds() { ids.clear(); }
     };
 
     using BpInfoPtr = std::unique_ptr<BpInfo>;
@@ -119,6 +133,8 @@ class ThreadContext : public ::ThreadContext
     void uninstallBp(BpInfoIt it);
     void delBp(BpInfoIt it);
 
+    virtual const std::vector<iris::MemorySpaceId> &getBpSpaceIds() const = 0;
+
 
     iris::IrisErrorCode instanceRegistryChanged(
             uint64_t esId, const iris::IrisValueMap &fields, uint64_t time,
@@ -132,11 +148,15 @@ class ThreadContext : public ::ThreadContext
     iris::IrisErrorCode breakpointHit(
             uint64_t esId, const iris::IrisValueMap &fields, uint64_t time,
             uint64_t sInstId, bool syncEc, std::string &error_message_out);
+    iris::IrisErrorCode semihostingEvent(
+            uint64_t esId, const iris::IrisValueMap &fields, uint64_t time,
+            uint64_t sInstId, bool syncEc, std::string &error_message_out);
 
     iris::EventStreamId regEventStreamId;
     iris::EventStreamId initEventStreamId;
     iris::EventStreamId timeEventStreamId;
     iris::EventStreamId breakpointEventStreamId;
+    iris::EventStreamId semihostingEventStreamId;
 
     mutable iris::IrisInstance client;
     iris::IrisCppAdapter &call() const { return client.irisCall(); }
@@ -147,7 +167,7 @@ class ThreadContext : public ::ThreadContext
 
   public:
     ThreadContext(::BaseCPU *cpu, int id, System *system,
-                  ::BaseTLB *dtb, ::BaseTLB *itb,
+                  ::BaseMMU *mmu, ::BaseISA *isa,
                   iris::IrisConnectionInterface *iris_if,
                   const std::string &iris_path);
     virtual ~ThreadContext();
@@ -181,12 +201,14 @@ class ThreadContext : public ::ThreadContext
     {
         return _dtb;
     }
-    CheckerCPU *
-    getCheckerCpuPtr() override
+    BaseMMU *
+    getMMUPtr() override
     {
-        panic("%s not implemented.", __FUNCTION__);
+        return _mmu;
     }
-    TheISA::Decoder *
+
+    CheckerCPU *getCheckerCpuPtr() override { return nullptr; }
+    ArmISA::Decoder *
     getDecoderPtr() override
     {
         panic("%s not implemented.", __FUNCTION__);
@@ -194,10 +216,10 @@ class ThreadContext : public ::ThreadContext
 
     System *getSystemPtr() override { return _cpu->system; }
 
-    Kernel::Statistics *
-    getKernelStats() override
+    BaseISA *
+    getIsaPtr() override
     {
-        panic("%s not implemented.", __FUNCTION__);
+        return _isa;
     }
 
     PortProxy &getPhysProxy() override { return *physProxy; }
@@ -221,12 +243,6 @@ class ThreadContext : public ::ThreadContext
     void suspend() override { setStatus(Suspended); }
     void halt() override { setStatus(Halted); }
 
-    void
-    dumpFuncProfile() override
-    {
-        panic("%s not implemented.", __FUNCTION__);
-    }
-
     void
     takeOverFrom(::ThreadContext *old_context) override
     {
@@ -235,12 +251,6 @@ class ThreadContext : public ::ThreadContext
 
     void regStats(const std::string &name) override {}
 
-    EndQuiesceEvent *
-    getQuiesceEvent() override
-    {
-        panic("%s not implemented.", __FUNCTION__);
-    }
-
     // Not necessarily the best location for these...
     // Having an extra function just to read these is obnoxious
     Tick
@@ -253,17 +263,6 @@ class ThreadContext : public ::ThreadContext
         panic("%s not implemented.", __FUNCTION__);
     }
 
-    void
-    profileClear() override
-    {
-        panic("%s not implemented.", __FUNCTION__);
-    }
-    void
-    profileSample() override
-    {
-        panic("%s not implemented.", __FUNCTION__);
-    }
-
     void
     copyArchRegs(::ThreadContext *tc) override
     {
@@ -273,7 +272,7 @@ class ThreadContext : public ::ThreadContext
     void
     clearArchRegs() override
     {
-        panic("%s not implemented.", __FUNCTION__);
+        warn("Ignoring clearArchRegs()");
     }
 
     //
@@ -287,11 +286,7 @@ class ThreadContext : public ::ThreadContext
         panic("%s not implemented.", __FUNCTION__);
     }
 
-    const VecRegContainer &
-    readVecReg(const RegId &reg) const override
-    {
-        panic("%s not implemented.", __FUNCTION__);
-    }
+    const VecRegContainer &readVecReg(const RegId &reg) const override;
     VecRegContainer &
     getWritableVecReg(const RegId &reg) override
     {
@@ -360,11 +355,7 @@ class ThreadContext : public ::ThreadContext
         panic("%s not implemented.", __FUNCTION__);
     }
 
-    const VecPredRegContainer &
-    readVecPredReg(const RegId &reg) const override
-    {
-        panic("%s not implemented.", __FUNCTION__);
-    }
+    const VecPredRegContainer &readVecPredReg(const RegId &reg) const override;
     VecPredRegContainer &
     getWritableVecPredReg(const RegId &reg) override
     {
@@ -374,7 +365,7 @@ class ThreadContext : public ::ThreadContext
     RegVal
     readCCReg(RegIndex reg_idx) const override
     {
-        panic("%s not implemented.", __FUNCTION__);
+        return readCCRegFlat(reg_idx);
     }
 
     void setIntReg(RegIndex reg_idx, RegVal val) override;
@@ -407,12 +398,17 @@ class ThreadContext : public ::ThreadContext
     void
     setCCReg(RegIndex reg_idx, RegVal val) override
     {
-        panic("%s not implemented.", __FUNCTION__);
+        setCCRegFlat(reg_idx, val);
     }
 
-    void pcStateNoRecord(const TheISA::PCState &val) override { pcState(val); }
+    void pcStateNoRecord(const ArmISA::PCState &val) override { pcState(val); }
     MicroPC microPC() const override { return 0; }
 
+    ArmISA::PCState pcState() const override;
+    void pcState(const ArmISA::PCState &val) override;
+    Addr instAddr() const override;
+    Addr nextInstAddr() const override;
+
     RegVal readMiscRegNoEffect(RegIndex misc_reg) const override;
     RegVal
     readMiscReg(RegIndex misc_reg) override
@@ -454,12 +450,6 @@ class ThreadContext : public ::ThreadContext
         panic("%s not implemented.", __FUNCTION__);
     }
 
-    void
-    syscall(Fault *fault) override
-    {
-        panic("%s not implemented.", __FUNCTION__);
-    }
-
     /** @{ */
     /**
      * Flat register interfaces
@@ -472,16 +462,8 @@ class ThreadContext : public ::ThreadContext
      * serialization code to access all registers.
      */
 
-    uint64_t
-    readIntRegFlat(RegIndex idx) const override
-    {
-        panic("%s not implemented.", __FUNCTION__);
-    }
-    void
-    setIntRegFlat(RegIndex idx, uint64_t val) override
-    {
-        panic("%s not implemented.", __FUNCTION__);
-    }
+    RegVal readIntRegFlat(RegIndex idx) const override;
+    void setIntRegFlat(RegIndex idx, uint64_t val) override;
 
     RegVal
     readFloatRegFlat(RegIndex idx) const override
@@ -494,11 +476,7 @@ class ThreadContext : public ::ThreadContext
         panic("%s not implemented.", __FUNCTION__);
     }
 
-    const VecRegContainer &
-    readVecRegFlat(RegIndex idx) const override
-    {
-        panic("%s not implemented.", __FUNCTION__);
-    }
+    const VecRegContainer &readVecRegFlat(RegIndex idx) const override;
     VecRegContainer &
     getWritableVecRegFlat(RegIndex idx) override
     {
@@ -522,11 +500,7 @@ class ThreadContext : public ::ThreadContext
         panic("%s not implemented.", __FUNCTION__);
     }
 
-    const VecPredRegContainer &
-    readVecPredRegFlat(RegIndex idx) const override
-    {
-        panic("%s not implemented.", __FUNCTION__);
-    }
+    const VecPredRegContainer &readVecPredRegFlat(RegIndex idx) const override;
     VecPredRegContainer &
     getWritableVecPredRegFlat(RegIndex idx) override
     {
@@ -538,18 +512,28 @@ class ThreadContext : public ::ThreadContext
         panic("%s not implemented.", __FUNCTION__);
     }
 
-    RegVal
-    readCCRegFlat(RegIndex idx) const override
+    RegVal readCCRegFlat(RegIndex idx) const override;
+    void setCCRegFlat(RegIndex idx, RegVal val) override;
+    /** @} */
+
+    // hardware transactional memory
+    void
+    htmAbortTransaction(uint64_t htm_uid, HtmFailureFaultCause cause) override
     {
         panic("%s not implemented.", __FUNCTION__);
     }
-    void
-    setCCRegFlat(RegIndex idx, RegVal val) override
+
+    BaseHTMCheckpointPtr &
+    getHtmCheckpointPtr() override
     {
         panic("%s not implemented.", __FUNCTION__);
     }
-    /** @} */
 
+    void
+    setHtmCheckpointPtr(BaseHTMCheckpointPtr cpt) override
+    {
+        panic("%s not implemented.", __FUNCTION__);
+    }
 };
 
 } // namespace Iris