/*
- * Copyright (c) 2010 ARM Limited
+ * Copyright (c) 2010, 2012-2013 ARM Limited
+ * Copyright (c) 2013 Advanced Micro Devices, Inc.
* All rights reserved
*
* The license below extends only to copyright in the software and shall
*/
#include "arch/arm/insts/misc.hh"
+#include "cpu/reg_class.hh"
std::string
MrsOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
ss << ", ";
bool foundPsr = false;
for (unsigned i = 0; i < numSrcRegs(); i++) {
- int idx = srcRegIdx(i);
- if (idx < Ctrl_Base_DepTag) {
+ RegIndex idx = srcRegIdx(i);
+ RegIndex rel_idx;
+ if (regIdxToClass(idx, &rel_idx) != MiscRegClass) {
continue;
}
- idx -= Ctrl_Base_DepTag;
- if (idx == MISCREG_CPSR) {
+ if (rel_idx == MISCREG_CPSR) {
ss << "cpsr";
foundPsr = true;
break;
}
- if (idx == MISCREG_SPSR) {
+ if (rel_idx == MISCREG_SPSR) {
ss << "spsr";
foundPsr = true;
break;
bool foundPsr = false;
for (unsigned i = 0; i < numDestRegs(); i++) {
int idx = destRegIdx(i);
- if (idx < Ctrl_Base_DepTag) {
+ if (idx < Misc_Reg_Base) {
continue;
}
- idx -= Ctrl_Base_DepTag;
+ idx -= Misc_Reg_Base;
if (idx == MISCREG_CPSR) {
os << "cpsr_";
foundPsr = true;
}
std::string
-RevOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+MrrcOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+{
+ std::stringstream ss;
+ printMnemonic(ss);
+ printReg(ss, dest);
+ ss << ", ";
+ printReg(ss, dest2);
+ ss << ", ";
+ printReg(ss, op1);
+ return ss.str();
+}
+
+std::string
+McrrOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+{
+ std::stringstream ss;
+ printMnemonic(ss);
+ printReg(ss, dest);
+ ss << ", ";
+ printReg(ss, op1);
+ ss << ", ";
+ printReg(ss, op2);
+ return ss.str();
+}
+
+std::string
+ImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+{
+ std::stringstream ss;
+ printMnemonic(ss);
+ ccprintf(ss, "#%d", imm);
+ return ss.str();
+}
+
+std::string
+RegImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+{
+ std::stringstream ss;
+ printMnemonic(ss);
+ printReg(ss, dest);
+ ccprintf(ss, ", #%d", imm);
+ return ss.str();
+}
+
+std::string
+RegRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss);
return ss.str();
}
+std::string
+RegRegImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+{
+ std::stringstream ss;
+ printMnemonic(ss);
+ printReg(ss, dest);
+ ss << ", ";
+ printReg(ss, op1);
+ ccprintf(ss, ", #%d", imm);
+ return ss.str();
+}
+
+std::string
+RegImmImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+{
+ std::stringstream ss;
+ printMnemonic(ss);
+ printReg(ss, dest);
+ ccprintf(ss, ", #%d, #%d", imm1, imm2);
+ return ss.str();
+}
+
+std::string
+RegRegImmImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+{
+ std::stringstream ss;
+ printMnemonic(ss);
+ printReg(ss, dest);
+ ss << ", ";
+ printReg(ss, op1);
+ ccprintf(ss, ", #%d, #%d", imm1, imm2);
+ return ss.str();
+}
+
std::string
RegImmRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{
printReg(ss, op1);
return ss.str();
}
+
+std::string
+UnknownOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+{
+ return csprintf("%-10s (inst %#08x)", "unknown", machInst);
+}