ARM: Explicitly keep track of the second destination for double loads/stores.

[gem5.git] / src / arch / arm / insts / pred_inst.hh

diff --git a/src/arch/arm/insts/pred_inst.hh b/src/arch/arm/insts/pred_inst.hh
index 6f9bd9dc29b71142ba5c3fbfdb0fb048943681be..8f92a2f26159419002c595d9b45c25bb49deedfb 100644 (file)
--- a/src/arch/arm/insts/pred_inst.hh
+++ b/src/arch/arm/insts/pred_inst.hh
@@ -1,4 +1,17 @@
-/* Copyright (c) 2007-2008 The Florida State University
+/*
+ * Copyright (c) 2010 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Copyright (c) 2007-2008 The Florida State University
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -41,6 +54,30 @@ rotate_imm(uint32_t immValue, int rotateValue)
             (immValue << (32 - (rotateValue & 31))));
 }
 
+static inline uint32_t
+modified_imm(uint8_t ctrlImm, uint8_t dataImm)
+{
+    uint32_t bigData = dataImm;
+    uint32_t bigCtrl = ctrlImm;
+    if (bigCtrl < 4) {
+        switch (bigCtrl) {
+          case 0:
+            return bigData;
+          case 1:
+            return bigData | (bigData << 16);
+          case 2:
+            return (bigData << 8) | (bigData << 24);
+          case 3:
+            return (bigData << 0) | (bigData << 8) |
+                   (bigData << 16) | (bigData << 24);
+        }
+    }
+    bigCtrl = (bigCtrl << 1) | ((bigData >> 7) & 0x1);
+    bigData |= (1 << 7);
+    return bigData << (32 - bigCtrl);
+}
+
+
 /**
  * Base class for predicated integer operations.
  */
@@ -51,7 +88,7 @@ class PredOp : public ArmStaticInst
     ConditionCode condCode;
 
     /// Constructor
-    PredOp(const char *mnem, MachInst _machInst, OpClass __opClass) :
+    PredOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
            ArmStaticInst(mnem, _machInst, __opClass),
            condCode((ConditionCode)(unsigned)machInst.condCode)
     {
@@ -66,19 +103,19 @@ class PredImmOp : public PredOp
     protected:
 
     uint32_t imm;
-    uint32_t rotate;
     uint32_t rotated_imm;
     uint32_t rotated_carry;
+    uint32_t rotate;
 
     /// Constructor
-    PredImmOp(const char *mnem, MachInst _machInst, OpClass __opClass) :
+    PredImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
               PredOp(mnem, _machInst, __opClass),
-              imm(machInst.imm), rotate(machInst.rotate << 1),
-              rotated_imm(0), rotated_carry(0)
+              imm(machInst.imm), rotated_imm(0), rotated_carry(0),
+              rotate(machInst.rotate << 1)
     {
         rotated_imm = rotate_imm(imm, rotate);
         if (rotate != 0)
-            rotated_carry = (rotated_imm >> 31) & 1;
+            rotated_carry = bits(rotated_imm, 31);
     }
 
     std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
@@ -95,7 +132,7 @@ class PredIntOp : public PredOp
     uint32_t shift;
 
     /// Constructor
-    PredIntOp(const char *mnem, MachInst _machInst, OpClass __opClass) :
+    PredIntOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
               PredOp(mnem, _machInst, __opClass),
               shift_size(machInst.shiftSize), shift(machInst.shift)
     {
@@ -104,6 +141,59 @@ class PredIntOp : public PredOp
     std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
 };
 
+class DataImmOp : public PredOp
+{
+  protected:
+    IntRegIndex dest, op1;
+    uint32_t imm;
+    // Whether the carry flag should be modified if that's an option for
+    // this instruction.
+    bool rotC;
+
+    DataImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
+              IntRegIndex _dest, IntRegIndex _op1, uint32_t _imm, bool _rotC) :
+        PredOp(mnem, _machInst, __opClass),
+        dest(_dest), op1(_op1), imm(_imm), rotC(_rotC)
+    {}
+
+    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+};
+
+class DataRegOp : public PredOp
+{
+  protected:
+    IntRegIndex dest, op1, op2;
+    int32_t shiftAmt;
+    ArmShiftType shiftType;
+
+    DataRegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
+              IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2,
+              int32_t _shiftAmt, ArmShiftType _shiftType) :
+        PredOp(mnem, _machInst, __opClass),
+        dest(_dest), op1(_op1), op2(_op2),
+        shiftAmt(_shiftAmt), shiftType(_shiftType)
+    {}
+
+    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+};
+
+class DataRegRegOp : public PredOp
+{
+  protected:
+    IntRegIndex dest, op1, op2, shift;
+    ArmShiftType shiftType;
+
+    DataRegRegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
+                 IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2,
+                 IntRegIndex _shift, ArmShiftType _shiftType) :
+        PredOp(mnem, _machInst, __opClass),
+        dest(_dest), op1(_op1), op2(_op2), shift(_shift),
+        shiftType(_shiftType)
+    {}
+
+    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+};
+
 /**
  * Base class for predicated macro-operations.
  */
@@ -115,7 +205,7 @@ class PredMacroOp : public PredOp
     StaticInstPtr * microOps;
 
     /// Constructor
-    PredMacroOp(const char *mnem, MachInst _machInst, OpClass __opClass) :
+    PredMacroOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
                 PredOp(mnem, _machInst, __opClass),
                 numMicroops(0)
     {
@@ -147,7 +237,7 @@ class PredMacroOp : public PredOp
 class PredMicroop : public PredOp
 {
     /// Constructor
-    PredMicroop(const char *mnem, MachInst _machInst, OpClass __opClass) :
+    PredMicroop(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
                 PredOp(mnem, _machInst, __opClass)
     {
         flags[IsMicroop] = true;