microLdrUopIop = InstObjParams('ldr_uop', 'MicroLdrUop',
'MicroMemOp',
{'memacc_code': microLdrUopCode,
- 'ea_code': 'EA = Rb + (up ? imm : -imm);',
+ 'ea_code': 'EA = URb + (up ? imm : -imm);',
'predicate_test': predicateTest},
['IsMicroop'])
microLdrFpUopIop = InstObjParams('ldrfp_uop', 'MicroLdrFpUop',
'MicroMemOp',
{'memacc_code': microLdrFpUopCode,
- 'ea_code':
- 'EA = Rb + (up ? imm : -imm);',
+ 'ea_code': vfpEnabledCheckCode +
+ 'EA = URb + (up ? imm : -imm);',
'predicate_test': predicateTest},
['IsMicroop'])
microLdrDBFpUopIop = InstObjParams('ldrfp_uop', 'MicroLdrDBFpUop',
'MicroMemOp',
{'memacc_code': microLdrFpUopCode,
- 'ea_code': '''
- EA = Rb + (up ? imm : -imm) +
+ 'ea_code': vfpEnabledCheckCode + '''
+ EA = URb + (up ? imm : -imm) +
(((CPSR)Cpsr).e ? 4 : 0);
''',
'predicate_test': predicateTest},
microLdrDTFpUopIop = InstObjParams('ldrfp_uop', 'MicroLdrDTFpUop',
'MicroMemOp',
{'memacc_code': microLdrFpUopCode,
- 'ea_code': '''
- EA = Rb + (up ? imm : -imm) -
+ 'ea_code': vfpEnabledCheckCode + '''
+ EA = URb + (up ? imm : -imm) -
(((CPSR)Cpsr).e ? 4 : 0);
''',
'predicate_test': predicateTest},
['IsMicroop'])
- microLdrRetUopCode = '''
- CPSR cpsr = Cpsr;
+ microRetUopCode = '''
+ CPSR old_cpsr = Cpsr;
SCTLR sctlr = Sctlr;
- uint32_t newCpsr =
- cpsrWriteByInstr(cpsr | CondCodes, Spsr, 0xF, true, sctlr.nmfi);
- Cpsr = ~CondCodesMask & newCpsr;
- CondCodes = CondCodesMask & newCpsr;
- IWNPC = cSwap(Mem.uw, cpsr.e) | ((Spsr & 0x20) ? 1 : 0);
+ old_cpsr.nz = CondCodesNZ;
+ old_cpsr.c = CondCodesC;
+ old_cpsr.v = CondCodesV;
+ old_cpsr.ge = CondCodesGE;
+
+ CPSR new_cpsr =
+ cpsrWriteByInstr(old_cpsr, Spsr, 0xF, true, sctlr.nmfi);
+ Cpsr = ~CondCodesMask & new_cpsr;
+ CondCodesNZ = new_cpsr.nz;
+ CondCodesC = new_cpsr.c;
+ CondCodesV = new_cpsr.v;
+ CondCodesGE = new_cpsr.ge;
+ IWNPC = cSwap(%s, old_cpsr.e) | ((Spsr & 0x20) ? 1 : 0);
+ NextItState = ((((CPSR)Spsr).it2 << 2) & 0xFC)
+ | (((CPSR)Spsr).it1 & 0x3);
+ SevMailbox = 1;
'''
+
microLdrRetUopIop = InstObjParams('ldr_ret_uop', 'MicroLdrRetUop',
'MicroMemOp',
- {'memacc_code': microLdrRetUopCode,
+ {'memacc_code':
+ microRetUopCode % 'Mem.uw',
'ea_code':
- 'EA = Rb + (up ? imm : -imm);',
+ 'EA = URb + (up ? imm : -imm);',
'predicate_test': condPredicateTest},
- ['IsMicroop'])
+ ['IsMicroop','IsNonSpeculative',
+ 'IsSerializeAfter'])
- microStrUopCode = "Mem = cSwap(Ra.uw, ((CPSR)Cpsr).e);"
+ microStrUopCode = "Mem = cSwap(URa.uw, ((CPSR)Cpsr).e);"
microStrUopIop = InstObjParams('str_uop', 'MicroStrUop',
'MicroMemOp',
{'memacc_code': microStrUopCode,
'postacc_code': "",
- 'ea_code': 'EA = Rb + (up ? imm : -imm);',
+ 'ea_code': 'EA = URb + (up ? imm : -imm);',
'predicate_test': predicateTest},
['IsMicroop'])
'MicroMemOp',
{'memacc_code': microStrFpUopCode,
'postacc_code': "",
- 'ea_code': 'EA = Rb + (up ? imm : -imm);',
+ 'ea_code': vfpEnabledCheckCode +
+ 'EA = URb + (up ? imm : -imm);',
'predicate_test': predicateTest},
['IsMicroop'])
'MicroMemOp',
{'memacc_code': microStrFpUopCode,
'postacc_code': "",
- 'ea_code': '''
- EA = Rb + (up ? imm : -imm) +
+ 'ea_code': vfpEnabledCheckCode + '''
+ EA = URb + (up ? imm : -imm) +
(((CPSR)Cpsr).e ? 4 : 0);
''',
'predicate_test': predicateTest},
'MicroMemOp',
{'memacc_code': microStrFpUopCode,
'postacc_code': "",
- 'ea_code': '''
- EA = Rb + (up ? imm : -imm) -
+ 'ea_code': vfpEnabledCheckCode + '''
+ EA = URb + (up ? imm : -imm) -
(((CPSR)Cpsr).e ? 4 : 0);
''',
'predicate_test': predicateTest},
let {{
exec_output = header_output = ''
- eaCode = 'EA = Ra + imm;'
+ eaCode = 'EA = URa + imm;'
for size in (1, 2, 3, 4, 6, 8, 12, 16):
# Set up the memory access.
{ 'mem_decl' : memDecl,
'size' : size,
'memacc_code' : loadMemAccCode,
- 'ea_code' : eaCode,
+ 'ea_code' : simdEnabledCheckCode + eaCode,
'predicate_test' : predicateTest },
[ 'IsMicroop', 'IsMemRef', 'IsLoad' ])
storeIop = InstObjParams('strneon%(size)d_uop' % subst,
{ 'mem_decl' : memDecl,
'size' : size,
'memacc_code' : storeMemAccCode,
- 'ea_code' : eaCode,
+ 'ea_code' : simdEnabledCheckCode + eaCode,
'predicate_test' : predicateTest },
[ 'IsMicroop', 'IsMemRef', 'IsStore' ])
let {{
microAddiUopIop = InstObjParams('addi_uop', 'MicroAddiUop',
'MicroIntImmOp',
- {'code': 'Ra = Rb + imm;',
+ {'code': 'URa = URb + imm;',
'predicate_test': predicateTest},
['IsMicroop'])
microAddUopIop = InstObjParams('add_uop', 'MicroAddUop',
- 'MicroIntOp',
- {'code': 'Ra = Rb + Rc;',
+ 'MicroIntRegOp',
+ {'code':
+ '''URa = URb + shift_rm_imm(URc, shiftAmt,
+ shiftType,
+ CondCodesC);
+ ''',
'predicate_test': predicateTest},
['IsMicroop'])
microSubiUopIop = InstObjParams('subi_uop', 'MicroSubiUop',
'MicroIntImmOp',
- {'code': 'Ra = Rb - imm;',
+ {'code': 'URa = URb - imm;',
'predicate_test': predicateTest},
['IsMicroop'])
+ microSubUopIop = InstObjParams('sub_uop', 'MicroSubUop',
+ 'MicroIntRegOp',
+ {'code':
+ '''URa = URb - shift_rm_imm(URc, shiftAmt,
+ shiftType,
+ CondCodesC);
+ ''',
+ 'predicate_test': predicateTest},
+ ['IsMicroop'])
+
+ microUopRegMovIop = InstObjParams('uopReg_uop', 'MicroUopRegMov',
+ 'MicroIntMov',
+ {'code': 'IWRa = URb;',
+ 'predicate_test': predicateTest},
+ ['IsMicroop'])
+
+ microUopRegMovRetIop = InstObjParams('movret_uop', 'MicroUopRegMovRet',
+ 'MicroIntMov',
+ {'code': microRetUopCode % 'URb',
+ 'predicate_test': predicateTest},
+ ['IsMicroop', 'IsNonSpeculative',
+ 'IsSerializeAfter'])
+
+ setPCCPSRDecl = '''
+ CPSR cpsrOrCondCodes = URc;
+ SCTLR sctlr = Sctlr;
+ pNPC = URa;
+ CPSR new_cpsr =
+ cpsrWriteByInstr(cpsrOrCondCodes, URb,
+ 0xF, true, sctlr.nmfi);
+ Cpsr = ~CondCodesMask & new_cpsr;
+ NextThumb = new_cpsr.t;
+ NextJazelle = new_cpsr.j;
+ NextItState = ((((CPSR)URb).it2 << 2) & 0xFC)
+ | (((CPSR)URb).it1 & 0x3);
+ CondCodesNZ = new_cpsr.nz;
+ CondCodesC = new_cpsr.c;
+ CondCodesV = new_cpsr.v;
+ CondCodesGE = new_cpsr.ge;
+ '''
+
+ microUopSetPCCPSRIop = InstObjParams('uopSet_uop', 'MicroUopSetPCCPSR',
+ 'MicroSetPCCPSR',
+ {'code': setPCCPSRDecl,
+ 'predicate_test': predicateTest},
+ ['IsMicroop'])
+
header_output = MicroIntImmDeclare.subst(microAddiUopIop) + \
MicroIntImmDeclare.subst(microSubiUopIop) + \
- MicroIntDeclare.subst(microAddUopIop)
+ MicroIntRegDeclare.subst(microAddUopIop) + \
+ MicroIntRegDeclare.subst(microSubUopIop) + \
+ MicroIntMovDeclare.subst(microUopRegMovIop) + \
+ MicroIntMovDeclare.subst(microUopRegMovRetIop) + \
+ MicroSetPCCPSRDeclare.subst(microUopSetPCCPSRIop)
+
decoder_output = MicroIntImmConstructor.subst(microAddiUopIop) + \
MicroIntImmConstructor.subst(microSubiUopIop) + \
- MicroIntConstructor.subst(microAddUopIop)
+ MicroIntRegConstructor.subst(microAddUopIop) + \
+ MicroIntRegConstructor.subst(microSubUopIop) + \
+ MicroIntMovConstructor.subst(microUopRegMovIop) + \
+ MicroIntMovConstructor.subst(microUopRegMovRetIop) + \
+ MicroSetPCCPSRConstructor.subst(microUopSetPCCPSRIop)
+
exec_output = PredOpExecute.subst(microAddiUopIop) + \
PredOpExecute.subst(microSubiUopIop) + \
- PredOpExecute.subst(microAddUopIop)
+ PredOpExecute.subst(microAddUopIop) + \
+ PredOpExecute.subst(microSubUopIop) + \
+ PredOpExecute.subst(microUopRegMovIop) + \
+ PredOpExecute.subst(microUopRegMovRetIop) + \
+ PredOpExecute.subst(microUopSetPCCPSRIop)
+
}};
let {{
projects / gem5.git / blobdiff