ARM: Break up condition codes into normal flags, saturation, and simd.

[gem5.git] / src / arch / arm / isa / insts / macromem.isa

diff --git a/src/arch/arm/isa/insts/macromem.isa b/src/arch/arm/isa/insts/macromem.isa
index 67d8da572f01340e7f5fe68430ad637e2ec65594..5007c85e57431d2c6c553bb556935a29d7a3011f 100644 (file)
--- a/src/arch/arm/isa/insts/macromem.isa
+++ b/src/arch/arm/isa/insts/macromem.isa
@@ -90,9 +90,12 @@ let {{
         CPSR cpsr = Cpsr;
         SCTLR sctlr = Sctlr;
         uint32_t newCpsr =
-            cpsrWriteByInstr(cpsr | CondCodes, Spsr, 0xF, true, sctlr.nmfi);
+            cpsrWriteByInstr(cpsr | CondCodesF | CondCodesQ | CondCodesGE,
+                             Spsr, 0xF, true, sctlr.nmfi);
         Cpsr = ~CondCodesMask & newCpsr;
-        CondCodes = CondCodesMask & newCpsr;
+        CondCodesF = CondCodesMaskF & newCpsr;
+        CondCodesQ = CondCodesMaskQ & newCpsr;
+        CondCodesGE = CondCodesMaskGE & newCpsr;
         IWNPC = cSwap(%s, cpsr.e) | ((Spsr & 0x20) ? 1 : 0);
         NextItState = ((((CPSR)Spsr).it2 << 2) & 0xFC)
                 | (((CPSR)Spsr).it1 & 0x3);
@@ -585,7 +588,7 @@ let {{
                                    {'code':
                                     '''URa = URb + shift_rm_imm(URc, shiftAmt,
                                                               shiftType,
-                                                              CondCodes<29:>);
+                                                              CondCodesF<29:>);
                                     ''',
                                     'predicate_test': predicateTest},
                                    ['IsMicroop'])
@@ -601,7 +604,7 @@ let {{
                                    {'code':
                                     '''URa = URb - shift_rm_imm(URc, shiftAmt,
                                                               shiftType,
-                                                              CondCodes<29:>);
+                                                              CondCodesF<29:>);
                                     ''',
                                     'predicate_test': predicateTest},
                                    ['IsMicroop'])
@@ -631,7 +634,9 @@ let {{
                     NextJazelle = ((CPSR)newCpsr).j;
                     NextItState = ((((CPSR)URb).it2 << 2) & 0xFC)
                                     | (((CPSR)URb).it1 & 0x3);
-                    CondCodes = CondCodesMask & newCpsr;
+                    CondCodesF = CondCodesMaskF & newCpsr;
+                    CondCodesQ = CondCodesMaskQ & newCpsr;
+                    CondCodesGE = CondCodesMaskGE & newCpsr;
                     '''
 
     microUopSetPCCPSRIop = InstObjParams('uopSet_uop', 'MicroUopSetPCCPSR',