ARM: Further break up condition code into NZ, C, V bits.

[gem5.git] / src / arch / arm / isa / insts / mult.isa

diff --git a/src/arch/arm/isa/insts/mult.isa b/src/arch/arm/isa/insts/mult.isa
index 31febe74700c8135c213170e1fb2db07cbe0f8e1..f4f8b867eef6fa7ef1a3a5de5a30b3bebd63dee6 100644 (file)
--- a/src/arch/arm/isa/insts/mult.isa
+++ b/src/arch/arm/isa/insts/mult.isa
@@ -52,7 +52,7 @@ let {{
         _in = (resTemp >> %(negBit)d) & 1;
         _iz = ((%(zType)s)resTemp == 0);
 
-        CondCodesF =  _in << 31 | _iz << 30 | (CondCodesF & 0x3FFFFFFF);
+        CondCodesNZ = (_in << 1) | _iz;
 
         DPRINTF(Arm, "(in, iz) = (%%d, %%d)\\n", _in, _iz);
        '''