arch,cpu: Enforce using accessors to get at src/destRegIdx.

[gem5.git] / src / arch / arm / isa / templates / branch.isa

diff --git a/src/arch/arm/isa/templates/branch.isa b/src/arch/arm/isa/templates/branch.isa
index c765cf7c372e88c73faf2488caa8a34fb932c920..cccd67f077ae2ad14c0fa81553b26e0104e4fa7e 100644 (file)
--- a/src/arch/arm/isa/templates/branch.isa
+++ b/src/arch/arm/isa/templates/branch.isa
@@ -61,7 +61,7 @@ def template BranchImmCondConstructor {{
         %(constructor)s;
         if (!(condCode == COND_AL || condCode == COND_UC)) {
             for (int x = 0; x < _numDestRegs; x++) {
-                _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+                setSrcRegIdx(_numSrcRegs++, destRegIdx(x));
             }
             flags[IsCondControl] = true;
         } else {
@@ -91,7 +91,7 @@ def template BranchRegCondConstructor {{
         %(constructor)s;
         if (!(condCode == COND_AL || condCode == COND_UC)) {
             for (int x = 0; x < _numDestRegs; x++) {
-                _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+                setSrcRegIdx(_numSrcRegs++, destRegIdx(x));
             }
             flags[IsCondControl] = true;
         } else {
@@ -125,7 +125,7 @@ def template BranchRegRegConstructor {{
         %(constructor)s;
         if (!(condCode == COND_AL || condCode == COND_UC)) {
             for (int x = 0; x < _numDestRegs; x++) {
-                _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+                setSrcRegIdx(_numSrcRegs++, destRegIdx(x));
             }
             flags[IsCondControl] = true;
         } else {