misc: Merge branch v20.1.0.3 hotfix into develop

[gem5.git] / src / arch / arm / isa.cc

diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index f4fabc16a33da90aae5406e21aef4fd257b71309..2429e5cb0421dbb7c1fc0483e2331ca994c0996e 100644 (file)
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010-2020 ARM Limited
+ * Copyright (c) 2010-2021 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -88,6 +88,7 @@ ISA::ISA(const Params &p) : BaseISA(p), system(NULL),
         haveLargeAsid64 = system->haveLargeAsid64();
         physAddrRange = system->physAddrRange();
         haveSVE = system->haveSVE();
+        haveVHE = system->haveVHE();
         havePAN = system->havePAN();
         haveSecEL2 = system->haveSecEL2();
         sveVL = system->sveVL();
@@ -100,6 +101,7 @@ ISA::ISA(const Params &p) : BaseISA(p), system(NULL),
         haveLargeAsid64 = false;
         physAddrRange = 32;  // dummy value
         haveSVE = true;
+        haveVHE = false;
         havePAN = false;
         haveSecEL2 = true;
         sveVL = p.sve_vl_se;
@@ -426,6 +428,10 @@ ISA::initID64(const ArmISAParams &p)
     miscRegs[MISCREG_ID_AA64ISAR0_EL1] = insertBits(
         miscRegs[MISCREG_ID_AA64ISAR0_EL1], 23, 20,
         haveLSE ? 0x2 : 0x0);
+    // VHE
+    miscRegs[MISCREG_ID_AA64MMFR1_EL1] = insertBits(
+        miscRegs[MISCREG_ID_AA64MMFR1_EL1], 11, 8,
+        haveVHE ? 0x1 : 0x0);
     // PAN
     miscRegs[MISCREG_ID_AA64MMFR1_EL1] = insertBits(
         miscRegs[MISCREG_ID_AA64MMFR1_EL1], 23, 20,