/*
- * Copyright (c) 2010-2018 ARM Limited
+ * Copyright (c) 2010-2019 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
*/
#include "arch/arm/isa.hh"
+
+#include "arch/arm/faults.hh"
+#include "arch/arm/interrupts.hh"
#include "arch/arm/pmu.hh"
#include "arch/arm/system.hh"
#include "arch/arm/tlb.hh"
#include "debug/Arm.hh"
#include "debug/MiscRegs.hh"
#include "dev/arm/generic_timer.hh"
+#include "dev/arm/gic_v3.hh"
+#include "dev/arm/gic_v3_cpu_interface.hh"
#include "params/ArmISA.hh"
#include "sim/faults.hh"
#include "sim/stat_control.hh"
: SimObject(p),
system(NULL),
_decoderFlavour(p->decoderFlavour),
- _vecRegRenameMode(p->vecRegRenameMode),
+ _vecRegRenameMode(Enums::Full),
pmu(p->pmu),
- impdefAsNop(p->impdef_nop)
+ haveGICv3CPUInterface(false),
+ impdefAsNop(p->impdef_nop),
+ afterStartup(false)
{
miscRegs[MISCREG_SCTLR_RST] = 0;
highestELIs64 = system->highestELIs64();
haveSecurity = system->haveSecurity();
haveLPAE = system->haveLPAE();
+ haveCrypto = system->haveCrypto();
haveVirtualization = system->haveVirtualization();
haveLargeAsid64 = system->haveLargeAsid64();
- physAddrRange64 = system->physAddrRange64();
+ physAddrRange = system->physAddrRange();
+ haveSVE = system->haveSVE();
+ havePAN = system->havePAN();
+ sveVL = system->sveVL();
+ haveLSE = system->haveLSE();
} else {
highestELIs64 = true; // ArmSystem::highestELIs64 does the same
haveSecurity = haveLPAE = haveVirtualization = false;
+ haveCrypto = true;
haveLargeAsid64 = false;
- physAddrRange64 = 32; // dummy value
+ physAddrRange = 32; // dummy value
+ haveSVE = true;
+ havePAN = false;
+ sveVL = p->sve_vl_se;
+ haveLSE = true;
}
+ // Initial rename mode depends on highestEL
+ const_cast<Enums::VecRegRenameMode&>(_vecRegRenameMode) =
+ highestELIs64 ? Enums::Full : Enums::Elem;
+
initializeMiscRegMetadata();
preUnflattenMiscReg();
SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST];
memset(miscRegs, 0, sizeof(miscRegs));
- // Initialize configurable default values
- miscRegs[MISCREG_MIDR] = p->midr;
- miscRegs[MISCREG_MIDR_EL1] = p->midr;
- miscRegs[MISCREG_VPIDR] = p->midr;
-
- miscRegs[MISCREG_ID_ISAR0] = p->id_isar0;
- miscRegs[MISCREG_ID_ISAR1] = p->id_isar1;
- miscRegs[MISCREG_ID_ISAR2] = p->id_isar2;
- miscRegs[MISCREG_ID_ISAR3] = p->id_isar3;
- miscRegs[MISCREG_ID_ISAR4] = p->id_isar4;
- miscRegs[MISCREG_ID_ISAR5] = p->id_isar5;
-
- miscRegs[MISCREG_ID_MMFR0] = p->id_mmfr0;
- miscRegs[MISCREG_ID_MMFR1] = p->id_mmfr1;
- miscRegs[MISCREG_ID_MMFR2] = p->id_mmfr2;
- miscRegs[MISCREG_ID_MMFR3] = p->id_mmfr3;
-
- if (FullSystem && system->highestELIs64()) {
- // Initialize AArch64 state
- clear64(p);
- return;
- }
+ initID32(p);
- // Initialize AArch32 state...
-
- CPSR cpsr = 0;
- cpsr.mode = MODE_USER;
- miscRegs[MISCREG_CPSR] = cpsr;
- updateRegMap(cpsr);
-
- SCTLR sctlr = 0;
- sctlr.te = (bool) sctlr_rst.te;
- sctlr.nmfi = (bool) sctlr_rst.nmfi;
- sctlr.v = (bool) sctlr_rst.v;
- sctlr.u = 1;
- sctlr.xp = 1;
- sctlr.rao2 = 1;
- sctlr.rao3 = 1;
- sctlr.rao4 = 0xf; // SCTLR[6:3]
- sctlr.uci = 1;
- sctlr.dze = 1;
- miscRegs[MISCREG_SCTLR_NS] = sctlr;
- miscRegs[MISCREG_SCTLR_RST] = sctlr_rst;
- miscRegs[MISCREG_HCPTR] = 0;
+ // We always initialize AArch64 ID registers even
+ // if we are in AArch32. This is done since if we
+ // are in SE mode we don't know if our ArmProcess is
+ // AArch32 or AArch64
+ initID64(p);
// Start with an event in the mailbox
miscRegs[MISCREG_SEV_MAILBOX] = 1;
(2 << 4) | // 5:4
(1 << 2) | // 3:2
0; // 1:0
+
miscRegs[MISCREG_NMRR_NS] =
(1 << 30) | // 31:30
(0 << 26) | // 27:26
(0 << 2) | // 3:2
0; // 1:0
+ if (FullSystem && system->highestELIs64()) {
+ // Initialize AArch64 state
+ clear64(p);
+ return;
+ }
+
+ // Initialize AArch32 state...
+ clear32(p, sctlr_rst);
+}
+
+void
+ISA::clear32(const ArmISAParams *p, const SCTLR &sctlr_rst)
+{
+ CPSR cpsr = 0;
+ cpsr.mode = MODE_USER;
+
+ if (FullSystem) {
+ miscRegs[MISCREG_MVBAR] = system->resetAddr();
+ }
+
+ miscRegs[MISCREG_CPSR] = cpsr;
+ updateRegMap(cpsr);
+
+ SCTLR sctlr = 0;
+ sctlr.te = (bool) sctlr_rst.te;
+ sctlr.nmfi = (bool) sctlr_rst.nmfi;
+ sctlr.v = (bool) sctlr_rst.v;
+ sctlr.u = 1;
+ sctlr.xp = 1;
+ sctlr.rao2 = 1;
+ sctlr.rao3 = 1;
+ sctlr.rao4 = 0xf; // SCTLR[6:3]
+ sctlr.uci = 1;
+ sctlr.dze = 1;
+ miscRegs[MISCREG_SCTLR_NS] = sctlr;
+ miscRegs[MISCREG_SCTLR_RST] = sctlr_rst;
+ miscRegs[MISCREG_HCPTR] = 0;
+
miscRegs[MISCREG_CPACR] = 0;
miscRegs[MISCREG_FPSID] = p->fpsid;
ISA::clear64(const ArmISAParams *p)
{
CPSR cpsr = 0;
- Addr rvbar = system->resetAddr64();
+ Addr rvbar = system->resetAddr();
switch (system->highestEL()) {
// Set initial EL to highest implemented EL using associated stack
// pointer (SP_ELx); set RVBAR_ELx to implementation defined reset
// Always non-secure
miscRegs[MISCREG_SCR_EL3] = 1;
}
+}
+
+void
+ISA::initID32(const ArmISAParams *p)
+{
+ // Initialize configurable default values
+
+ uint32_t midr;
+ if (p->midr != 0x0)
+ midr = p->midr;
+ else if (highestELIs64)
+ // Cortex-A57 TRM r0p0 MIDR
+ midr = 0x410fd070;
+ else
+ // Cortex-A15 TRM r0p0 MIDR
+ midr = 0x410fc0f0;
+
+ miscRegs[MISCREG_MIDR] = midr;
+ miscRegs[MISCREG_MIDR_EL1] = midr;
+ miscRegs[MISCREG_VPIDR] = midr;
+ miscRegs[MISCREG_ID_ISAR0] = p->id_isar0;
+ miscRegs[MISCREG_ID_ISAR1] = p->id_isar1;
+ miscRegs[MISCREG_ID_ISAR2] = p->id_isar2;
+ miscRegs[MISCREG_ID_ISAR3] = p->id_isar3;
+ miscRegs[MISCREG_ID_ISAR4] = p->id_isar4;
+ miscRegs[MISCREG_ID_ISAR5] = p->id_isar5;
+
+ miscRegs[MISCREG_ID_MMFR0] = p->id_mmfr0;
+ miscRegs[MISCREG_ID_MMFR1] = p->id_mmfr1;
+ miscRegs[MISCREG_ID_MMFR2] = p->id_mmfr2;
+ miscRegs[MISCREG_ID_MMFR3] = p->id_mmfr3;
+
+ miscRegs[MISCREG_ID_ISAR5] = insertBits(
+ miscRegs[MISCREG_ID_ISAR5], 19, 4,
+ haveCrypto ? 0x1112 : 0x0);
+}
+
+void
+ISA::initID64(const ArmISAParams *p)
+{
// Initialize configurable id registers
miscRegs[MISCREG_ID_AA64AFR0_EL1] = p->id_aa64afr0_el1;
miscRegs[MISCREG_ID_AA64AFR1_EL1] = p->id_aa64afr1_el1;
miscRegs[MISCREG_ID_AA64ISAR1_EL1] = p->id_aa64isar1_el1;
miscRegs[MISCREG_ID_AA64MMFR0_EL1] = p->id_aa64mmfr0_el1;
miscRegs[MISCREG_ID_AA64MMFR1_EL1] = p->id_aa64mmfr1_el1;
+ miscRegs[MISCREG_ID_AA64MMFR2_EL1] = p->id_aa64mmfr2_el1;
miscRegs[MISCREG_ID_DFR0_EL1] =
(p->pmu ? 0x03000000ULL : 0); // Enable PMUv3
miscRegs[MISCREG_ID_DFR0] = miscRegs[MISCREG_ID_DFR0_EL1];
+ // SVE
+ miscRegs[MISCREG_ID_AA64ZFR0_EL1] = 0; // SVEver 0
+ if (haveSecurity) {
+ miscRegs[MISCREG_ZCR_EL3] = sveVL - 1;
+ } else if (haveVirtualization) {
+ miscRegs[MISCREG_ZCR_EL2] = sveVL - 1;
+ } else {
+ miscRegs[MISCREG_ZCR_EL1] = sveVL - 1;
+ }
+
// Enforce consistency with system-level settings...
// EL3
miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits(
miscRegs[MISCREG_ID_AA64PFR0_EL1], 11, 8,
haveVirtualization ? 0x2 : 0x0);
+ // SVE
+ miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits(
+ miscRegs[MISCREG_ID_AA64PFR0_EL1], 35, 32,
+ haveSVE ? 0x1 : 0x0);
// Large ASID support
miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits(
miscRegs[MISCREG_ID_AA64MMFR0_EL1], 7, 4,
// Physical address size
miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits(
miscRegs[MISCREG_ID_AA64MMFR0_EL1], 3, 0,
- encodePhysAddrRange64(physAddrRange64));
+ encodePhysAddrRange64(physAddrRange));
+ // Crypto
+ miscRegs[MISCREG_ID_AA64ISAR0_EL1] = insertBits(
+ miscRegs[MISCREG_ID_AA64ISAR0_EL1], 19, 4,
+ haveCrypto ? 0x1112 : 0x0);
+ // LSE
+ miscRegs[MISCREG_ID_AA64ISAR0_EL1] = insertBits(
+ miscRegs[MISCREG_ID_AA64ISAR0_EL1], 23, 20,
+ haveLSE ? 0x2 : 0x0);
+ // PAN
+ miscRegs[MISCREG_ID_AA64MMFR1_EL1] = insertBits(
+ miscRegs[MISCREG_ID_AA64MMFR1_EL1], 23, 20,
+ havePAN ? 0x1 : 0x0);
}
-MiscReg
+void
+ISA::startup(ThreadContext *tc)
+{
+ pmu->setThreadContext(tc);
+
+ if (system) {
+ Gicv3 *gicv3 = dynamic_cast<Gicv3 *>(system->getGIC());
+ if (gicv3) {
+ haveGICv3CPUInterface = true;
+ gicv3CpuInterface.reset(gicv3->getCPUInterface(tc->contextId()));
+ gicv3CpuInterface->setISA(this);
+ gicv3CpuInterface->setThreadContext(tc);
+ }
+ }
+
+ afterStartup = true;
+}
+
+
+RegVal
ISA::readMiscRegNoEffect(int misc_reg) const
{
assert(misc_reg < NumMiscRegs);
}
-MiscReg
+RegVal
ISA::readMiscReg(int misc_reg, ThreadContext *tc)
{
CPSR cpsr = 0;
switch (unflattenMiscReg(misc_reg)) {
case MISCREG_HCR:
- {
+ case MISCREG_HCR2:
if (!haveVirtualization)
return 0;
- else
- return readMiscRegNoEffect(MISCREG_HCR);
- }
+ break;
case MISCREG_CPACR:
{
const uint32_t ones = (uint32_t)(-1);
if (!nsacr.cp11) cpacrMask.cp11 = 0;
}
}
- MiscReg val = readMiscRegNoEffect(MISCREG_CPACR);
+ RegVal val = readMiscRegNoEffect(MISCREG_CPACR);
val &= cpacrMask;
DPRINTF(MiscRegs, "Reading misc reg %s: %#x\n",
miscRegName[misc_reg], val);
return val;
}
case MISCREG_MPIDR:
- cpsr = readMiscRegNoEffect(MISCREG_CPSR);
- scr = readMiscRegNoEffect(MISCREG_SCR);
- if ((cpsr.mode == MODE_HYP) || inSecureState(scr, cpsr)) {
- return getMPIDR(system, tc);
- } else {
- return readMiscReg(MISCREG_VMPIDR, tc);
- }
- break;
case MISCREG_MPIDR_EL1:
- // @todo in the absence of v8 virtualization support just return MPIDR_EL1
- return getMPIDR(system, tc) & 0xffffffff;
+ return readMPIDR(system, tc);
case MISCREG_VMPIDR:
+ case MISCREG_VMPIDR_EL2:
// top bit defined as RES1
return readMiscRegNoEffect(misc_reg) | 0x80000000;
case MISCREG_ID_AFR0: // not implemented, so alias MIDR
const uint32_t ones = (uint32_t)(-1);
FPSCR fpscrMask = 0;
fpscrMask.len = ones;
+ fpscrMask.fz16 = ones;
fpscrMask.stride = ones;
fpscrMask.rMode = ones;
fpscrMask.fz = ones;
{
return miscRegs[MISCREG_CPSR] & 0xc;
}
+ case MISCREG_PAN:
+ {
+ return miscRegs[MISCREG_CPSR] & 0x400000;
+ }
case MISCREG_L2CTLR:
{
// mostly unimplemented, just set NumCPUs field from sim and return
case MISCREG_DBGDSCRint:
return 0;
case MISCREG_ISR:
- return tc->getCpuPtr()->getInterruptController(tc->threadId())->getISR(
- readMiscRegNoEffect(MISCREG_HCR),
- readMiscRegNoEffect(MISCREG_CPSR),
- readMiscRegNoEffect(MISCREG_SCR));
+ {
+ auto ic = dynamic_cast<ArmISA::Interrupts *>(
+ tc->getCpuPtr()->getInterruptController(tc->threadId()));
+ return ic->getISR(
+ readMiscRegNoEffect(MISCREG_HCR),
+ readMiscRegNoEffect(MISCREG_CPSR),
+ readMiscRegNoEffect(MISCREG_SCR));
+ }
case MISCREG_ISR_EL1:
- return tc->getCpuPtr()->getInterruptController(tc->threadId())->getISR(
- readMiscRegNoEffect(MISCREG_HCR_EL2),
- readMiscRegNoEffect(MISCREG_CPSR),
- readMiscRegNoEffect(MISCREG_SCR_EL3));
+ {
+ auto ic = dynamic_cast<ArmISA::Interrupts *>(
+ tc->getCpuPtr()->getInterruptController(tc->threadId()));
+ return ic->getISR(
+ readMiscRegNoEffect(MISCREG_HCR_EL2),
+ readMiscRegNoEffect(MISCREG_CPSR),
+ readMiscRegNoEffect(MISCREG_SCR_EL3));
+ }
case MISCREG_DCZID_EL0:
return 0x04; // DC ZVA clear 64-byte chunks
case MISCREG_HCPTR:
{
- MiscReg val = readMiscRegNoEffect(misc_reg);
+ RegVal val = readMiscRegNoEffect(misc_reg);
// The trap bit associated with CP14 is defined as RAZ
val &= ~(1 << 14);
// If a CP bit in NSACR is 0 then the corresponding bit in
inSecureState(readMiscRegNoEffect(MISCREG_SCR),
readMiscRegNoEffect(MISCREG_CPSR));
if (!secure_lookup) {
- MiscReg mask = readMiscRegNoEffect(MISCREG_NSACR);
+ RegVal mask = readMiscRegNoEffect(MISCREG_NSACR);
val |= (mask ^ 0x7FFF) & 0xBFFF;
}
// Set the bits for unimplemented coprocessors to RAO/WI
return readMiscRegNoEffect(MISCREG_DFAR_S);
case MISCREG_HIFAR: // alias for secure IFAR
return readMiscRegNoEffect(MISCREG_IFAR_S);
- case MISCREG_HVBAR: // bottom bits reserved
- return readMiscRegNoEffect(MISCREG_HVBAR) & 0xFFFFFFE0;
- case MISCREG_SCTLR:
- return (readMiscRegNoEffect(misc_reg) & 0x72DD39FF) | 0x00C00818;
- case MISCREG_SCTLR_EL1:
- return (readMiscRegNoEffect(misc_reg) & 0x37DDDBBF) | 0x30D00800;
- case MISCREG_SCTLR_EL2:
- case MISCREG_SCTLR_EL3:
- case MISCREG_HSCTLR:
- return (readMiscRegNoEffect(misc_reg) & 0x32CD183F) | 0x30C50830;
case MISCREG_ID_PFR0:
// !ThumbEE | !Jazelle | Thumb | ARM
| (haveTimer ? 0x00010000 : 0x0);
}
case MISCREG_ID_AA64PFR0_EL1:
- return 0x0000000000000002 // AArch{64,32} supported at EL0
- | 0x0000000000000020 // EL1
- | (haveVirtualization ? 0x0000000000000200 : 0) // EL2
- | (haveSecurity ? 0x0000000000002000 : 0); // EL3
+ return 0x0000000000000002 | // AArch{64,32} supported at EL0
+ 0x0000000000000020 | // EL1
+ (haveVirtualization ? 0x0000000000000200 : 0) | // EL2
+ (haveSecurity ? 0x0000000000002000 : 0) | // EL3
+ (haveSVE ? 0x0000000100000000 : 0) | // SVE
+ (haveGICv3CPUInterface ? 0x0000000001000000 : 0);
case MISCREG_ID_AA64PFR1_EL1:
return 0; // bits [63:0] RES0 (reserved for future use)
// Generic Timer registers
+ case MISCREG_CNTHV_CTL_EL2:
+ case MISCREG_CNTHV_CVAL_EL2:
+ case MISCREG_CNTHV_TVAL_EL2:
case MISCREG_CNTFRQ ... MISCREG_CNTHP_CTL:
case MISCREG_CNTPCT ... MISCREG_CNTHP_CVAL:
case MISCREG_CNTKCTL_EL1 ... MISCREG_CNTV_CVAL_EL0:
case MISCREG_CNTVOFF_EL2 ... MISCREG_CNTPS_CVAL_EL1:
return getGenericTimer(tc).readMiscReg(misc_reg);
+ case MISCREG_ICC_AP0R0 ... MISCREG_ICH_LRC15:
+ case MISCREG_ICC_PMR_EL1 ... MISCREG_ICC_IGRPEN1_EL3:
+ case MISCREG_ICH_AP0R0_EL2 ... MISCREG_ICH_LR15_EL2:
+ return getGICv3CPUInterface(tc).readMiscReg(misc_reg);
+
default:
break;
}
void
-ISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val)
+ISA::setMiscRegNoEffect(int misc_reg, RegVal val)
{
assert(misc_reg < NumMiscRegs);
}
void
-ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
+ISA::setMiscReg(int misc_reg, RegVal val, ThreadContext *tc)
{
- MiscReg newVal = val;
+ RegVal newVal = val;
bool secure_lookup;
SCR scr;
getDTBPtr(tc)->invalidateMiscReg();
}
+ if (cpsr.pan != old_cpsr.pan) {
+ getDTBPtr(tc)->invalidateMiscReg();
+ }
+
DPRINTF(Arm, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n",
miscRegs[misc_reg], cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode);
PCState pc = tc->pcState();
pc.nextThumb(cpsr.t);
pc.nextJazelle(cpsr.j);
+ pc.illegalExec(cpsr.il == 1);
+
+ tc->getDecoderPtr()->setSveLen((getCurSveVecLenInBits(tc) >> 7) - 1);
// Follow slightly different semantics if a CheckerCPU object
// is connected
}
}
- MiscReg old_val = readMiscRegNoEffect(MISCREG_CPACR);
+ RegVal old_val = readMiscRegNoEffect(MISCREG_CPACR);
newVal &= cpacrMask;
newVal |= old_val & ~cpacrMask;
DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n",
miscRegName[misc_reg], newVal);
}
break;
+ case MISCREG_CPACR_EL1:
+ {
+ const uint32_t ones = (uint32_t)(-1);
+ CPACR cpacrMask = 0;
+ cpacrMask.tta = ones;
+ cpacrMask.fpen = ones;
+ if (haveSVE) {
+ cpacrMask.zen = ones;
+ }
+ newVal &= cpacrMask;
+ DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n",
+ miscRegName[misc_reg], newVal);
+ }
+ break;
case MISCREG_CPTR_EL2:
{
const uint32_t ones = (uint32_t)(-1);
cptrMask.tcpac = ones;
cptrMask.tta = ones;
cptrMask.tfp = ones;
+ if (haveSVE) {
+ cptrMask.tz = ones;
+ }
newVal &= cptrMask;
cptrMask = 0;
cptrMask.res1_13_12_el2 = ones;
- cptrMask.res1_9_0_el2 = ones;
+ cptrMask.res1_7_0_el2 = ones;
+ if (!haveSVE) {
+ cptrMask.res1_8_el2 = ones;
+ }
+ cptrMask.res1_9_el2 = ones;
newVal |= cptrMask;
DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n",
miscRegName[misc_reg], newVal);
cptrMask.tcpac = ones;
cptrMask.tta = ones;
cptrMask.tfp = ones;
+ if (haveSVE) {
+ cptrMask.ez = ones;
+ }
newVal &= cptrMask;
DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n",
miscRegName[misc_reg], newVal);
fpscrMask.ixe = ones;
fpscrMask.ide = ones;
fpscrMask.len = ones;
+ fpscrMask.fz16 = ones;
fpscrMask.stride = ones;
fpscrMask.rMode = ones;
fpscrMask.fz = ones;
const uint32_t ones = (uint32_t)(-1);
FPSCR fpscrMask = 0;
fpscrMask.len = ones;
+ fpscrMask.fz16 = ones;
fpscrMask.stride = ones;
fpscrMask.rMode = ones;
fpscrMask.fz = ones;
}
break;
case MISCREG_HCR:
- {
+ case MISCREG_HCR2:
if (!haveVirtualization)
return;
- }
- break;
+ break;
case MISCREG_IFSR:
{
// ARM ARM (ARM DDI 0406C.b) B4.1.96
SCTLR sctlr = miscRegs[sctlr_idx];
SCTLR new_sctlr = newVal;
new_sctlr.nmfi = ((bool)sctlr.nmfi) && !haveVirtualization;
- miscRegs[sctlr_idx] = (MiscReg)new_sctlr;
+ miscRegs[sctlr_idx] = (RegVal)new_sctlr;
getITBPtr(tc)->invalidateMiscReg();
getDTBPtr(tc)->invalidateMiscReg();
}
case MISCREG_ID_AA64ISAR1_EL1:
case MISCREG_ID_AA64MMFR0_EL1:
case MISCREG_ID_AA64MMFR1_EL1:
+ case MISCREG_ID_AA64MMFR2_EL1:
case MISCREG_ID_AA64PFR0_EL1:
case MISCREG_ID_AA64PFR1_EL1:
// ID registers are constants.
scr = readMiscReg(MISCREG_SCR, tc);
TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns,
- mbits(newVal, 31,12), false);
+ mbits(newVal, 31,12));
tlbiOp(tc);
return;
scr = readMiscReg(MISCREG_SCR, tc);
TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns,
- mbits(newVal, 31,12), false);
+ mbits(newVal, 31,12));
tlbiOp.broadcast(tc);
return;
assert32(tc);
scr = readMiscReg(MISCREG_SCR, tc);
- TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns,
- mbits(newVal, 31,12), true);
+ TLBIMVAA tlbiOp(EL2, haveSecurity && !scr.ns,
+ mbits(newVal, 31,12));
tlbiOp(tc);
return;
assert32(tc);
scr = readMiscReg(MISCREG_SCR, tc);
- TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns,
- mbits(newVal, 31,12), true);
+ TLBIMVAA tlbiOp(EL2, haveSecurity && !scr.ns,
+ mbits(newVal, 31,12));
tlbiOp.broadcast(tc);
return;
{
assert32(tc);
- TLBIALLN tlbiOp(EL1, false);
+ TLBIALLN tlbiOp(EL1);
tlbiOp(tc);
return;
}
{
assert32(tc);
- TLBIALLN tlbiOp(EL1, false);
+ TLBIALLN tlbiOp(EL1);
tlbiOp.broadcast(tc);
return;
}
{
assert32(tc);
- TLBIALLN tlbiOp(EL1, true);
+ TLBIALLN tlbiOp(EL2);
tlbiOp(tc);
return;
}
{
assert32(tc);
- TLBIALLN tlbiOp(EL1, true);
+ TLBIALLN tlbiOp(EL2);
tlbiOp.broadcast(tc);
return;
}
tlbiOp.broadcast(tc);
return;
}
- // @todo: uncomment this to enable Virtualization
- // case MISCREG_TLBI_ALLE2IS:
- // case MISCREG_TLBI_ALLE2:
+ // AArch64 TLB Invalidate All, EL2, Inner Shareable
+ case MISCREG_TLBI_ALLE2:
+ case MISCREG_TLBI_ALLE2IS:
+ {
+ assert64(tc);
+ scr = readMiscReg(MISCREG_SCR, tc);
+
+ TLBIALL tlbiOp(EL2, haveSecurity && !scr.ns);
+ tlbiOp(tc);
+ return;
+ }
// AArch64 TLB Invalidate All, EL1
case MISCREG_TLBI_ALLE1:
case MISCREG_TLBI_VMALLE1:
scr = readMiscReg(MISCREG_SCR, tc);
TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns,
- static_cast<Addr>(bits(newVal, 43, 0)) << 12, false);
+ static_cast<Addr>(bits(newVal, 43, 0)) << 12);
tlbiOp(tc);
return;
scr = readMiscReg(MISCREG_SCR, tc);
TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns,
- static_cast<Addr>(bits(newVal, 43, 0)) << 12, false);
+ static_cast<Addr>(bits(newVal, 43, 0)) << 12);
tlbiOp.broadcast(tc);
return;
inSecureState(readMiscRegNoEffect(MISCREG_SCR),
readMiscRegNoEffect(MISCREG_CPSR));
if (!secure_lookup) {
- MiscReg oldValue = readMiscRegNoEffect(MISCREG_HCPTR);
- MiscReg mask = (readMiscRegNoEffect(MISCREG_NSACR) ^ 0x7FFF) & 0xBFFF;
+ RegVal oldValue = readMiscRegNoEffect(MISCREG_HCPTR);
+ RegVal mask =
+ (readMiscRegNoEffect(MISCREG_NSACR) ^ 0x7FFF) & 0xBFFF;
newVal = (newVal & ~mask) | (oldValue & mask);
}
break;
// done in the same mode the core is running in. NOTE: This
// can't be an atomic translation because that causes problems
// with unexpected atomic snoop requests.
- warn("Translating via MISCREG(%d) in functional mode! Fix Me!\n", misc_reg);
- Request req(0, val, 0, flags, Request::funcMasterId,
- tc->pcState().pc(), tc->contextId());
+ warn("Translating via %s in functional mode! Fix Me!\n",
+ miscRegName[misc_reg]);
+
+ auto req = std::make_shared<Request>(
+ 0, val, 0, flags, Request::funcMasterId,
+ tc->pcState().pc(), tc->contextId());
+
fault = getDTBPtr(tc)->translateFunctional(
- &req, tc, mode, tranType);
+ req, tc, mode, tranType);
+
TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR);
HCR hcr = readMiscRegNoEffect(MISCREG_HCR);
- MiscReg newVal;
+ RegVal newVal;
if (fault == NoFault) {
- Addr paddr = req.getPaddr();
+ Addr paddr = req->getPaddr();
if (haveLPAE && (ttbcr.eae || tranType & TLB::HypMode ||
((tranType & TLB::S1S2NsTran) && hcr.vm) )) {
newVal = (paddr & mask(39, 12)) |
misc_reg = MISCREG_CPSR;
}
break;
+ case MISCREG_PAN:
+ {
+ // PAN is affecting data accesses
+ getDTBPtr(tc)->invalidateMiscReg();
+
+ CPSR cpsr = miscRegs[MISCREG_CPSR];
+ cpsr.pan = (uint8_t) ((CPSR) newVal).pan;
+ newVal = cpsr;
+ misc_reg = MISCREG_CPSR;
+ }
+ break;
case MISCREG_AT_S1E1R_Xt:
case MISCREG_AT_S1E1W_Xt:
case MISCREG_AT_S1E0R_Xt:
case MISCREG_AT_S1E3R_Xt:
case MISCREG_AT_S1E3W_Xt:
{
- RequestPtr req = new Request;
+ RequestPtr req = std::make_shared<Request>();
Request::Flags flags = 0;
BaseTLB::Mode mode = BaseTLB::Read;
TLB::ArmTranslationType tranType = TLB::NormalTran;
// done in the same mode the core is running in. NOTE: This
// can't be an atomic translation because that causes problems
// with unexpected atomic snoop requests.
- warn("Translating via MISCREG(%d) in functional mode! Fix Me!\n", misc_reg);
+ warn("Translating via %s in functional mode! Fix Me!\n",
+ miscRegName[misc_reg]);
+
req->setVirt(0, val, 0, flags, Request::funcMasterId,
tc->pcState().pc());
req->setContext(tc->contextId());
fault = getDTBPtr(tc)->translateFunctional(req, tc, mode,
tranType);
- MiscReg newVal;
+ RegVal newVal;
if (fault == NoFault) {
Addr paddr = req->getPaddr();
uint64_t attr = getDTBPtr(tc)->getAttr();
"MISCREG: Translated addr %#x fault fsr %#x: PAR: %#x\n",
val, fsr, newVal);
}
- delete req;
setMiscRegNoEffect(MISCREG_PAR_EL1, newVal);
return;
}
case MISCREG_SPSR_EL3:
case MISCREG_SPSR_EL2:
case MISCREG_SPSR_EL1:
- // Force bits 23:21 to 0
- newVal = val & ~(0x7 << 21);
- break;
+ {
+ RegVal spsr_mask = havePAN ?
+ ~(0x5 << 21) : ~(0x7 << 21);
+
+ newVal = val & spsr_mask;
+ break;
+ }
case MISCREG_L2CTLR:
warn("miscreg L2CTLR (%s) written with %#x. ignored...\n",
miscRegName[misc_reg], uint32_t(val));
break;
// Generic Timer registers
+ case MISCREG_CNTHV_CTL_EL2:
+ case MISCREG_CNTHV_CVAL_EL2:
+ case MISCREG_CNTHV_TVAL_EL2:
case MISCREG_CNTFRQ ... MISCREG_CNTHP_CTL:
case MISCREG_CNTPCT ... MISCREG_CNTHP_CVAL:
case MISCREG_CNTKCTL_EL1 ... MISCREG_CNTV_CVAL_EL0:
case MISCREG_CNTVOFF_EL2 ... MISCREG_CNTPS_CVAL_EL1:
getGenericTimer(tc).setMiscReg(misc_reg, newVal);
break;
+ case MISCREG_ICC_AP0R0 ... MISCREG_ICH_LRC15:
+ case MISCREG_ICC_PMR_EL1 ... MISCREG_ICC_IGRPEN1_EL3:
+ case MISCREG_ICH_AP0R0_EL2 ... MISCREG_ICH_LR15_EL2:
+ getGICv3CPUInterface(tc).setMiscReg(misc_reg, newVal);
+ return;
+ case MISCREG_ZCR_EL3:
+ case MISCREG_ZCR_EL2:
+ case MISCREG_ZCR_EL1:
+ tc->getDecoderPtr()->setSveLen(
+ (getCurSveVecLenInBits(tc) >> 7) - 1);
+ break;
}
}
setMiscRegNoEffect(misc_reg, newVal);
}
timer.reset(new GenericTimerISA(*generic_timer, tc->contextId()));
+ timer->setThreadContext(tc);
+
return *timer.get();
}
+BaseISADevice &
+ISA::getGICv3CPUInterface(ThreadContext *tc)
+{
+ panic_if(!gicv3CpuInterface, "GICV3 cpu interface is not registered!");
+ return *gicv3CpuInterface.get();
}
+unsigned
+ISA::getCurSveVecLenInBits(ThreadContext *tc) const
+{
+ if (!FullSystem) {
+ return sveVL * 128;
+ }
+
+ panic_if(!tc,
+ "A ThreadContext is needed to determine the SVE vector length "
+ "in full-system mode");
+
+ CPSR cpsr = miscRegs[MISCREG_CPSR];
+ ExceptionLevel el = (ExceptionLevel) (uint8_t) cpsr.el;
+
+ unsigned len = 0;
+
+ if (el == EL1 || (el == EL0 && !ELIsInHost(tc, el))) {
+ len = static_cast<ZCR>(miscRegs[MISCREG_ZCR_EL1]).len;
+ }
+
+ if (el == EL2 || (el == EL0 && ELIsInHost(tc, el))) {
+ len = static_cast<ZCR>(miscRegs[MISCREG_ZCR_EL2]).len;
+ } else if (haveVirtualization && !inSecureState(tc) &&
+ (el == EL0 || el == EL1)) {
+ len = std::min(
+ len,
+ static_cast<unsigned>(
+ static_cast<ZCR>(miscRegs[MISCREG_ZCR_EL2]).len));
+ }
+
+ if (el == EL3) {
+ len = static_cast<ZCR>(miscRegs[MISCREG_ZCR_EL3]).len;
+ } else if (haveSecurity) {
+ len = std::min(
+ len,
+ static_cast<unsigned>(
+ static_cast<ZCR>(miscRegs[MISCREG_ZCR_EL3]).len));
+ }
+
+ len = std::min(len, sveVL - 1);
+
+ return (len + 1) * 128;
+}
+
+void
+ISA::zeroSveVecRegUpperPart(VecRegContainer &vc, unsigned eCount)
+{
+ auto vv = vc.as<uint64_t>();
+ for (int i = 2; i < eCount; ++i) {
+ vv[i] = 0;
+ }
+}
+
+} // namespace ArmISA
+
ArmISA::ISA *
ArmISAParams::create()
{
projects / gem5.git / blobdiff