SPARC: Get rid of the copy/pasted StackTrace stolen from Alpha.

[gem5.git] / src / arch / arm / isa.hh

diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh
index ec6479f5008753e5654c2d8f42e5699c8b0282f0..8318417f59c3ea59add17099036f29ff41a0b4cf 100644 (file)
--- a/src/arch/arm/isa.hh
+++ b/src/arch/arm/isa.hh
@@ -91,88 +91,11 @@ namespace ArmISA
         }
 
       public:
-        void clear()
-        {
-            SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST];
-
-            memset(miscRegs, 0, sizeof(miscRegs));
-            CPSR cpsr = 0;
-            cpsr.mode = MODE_USER;
-            miscRegs[MISCREG_CPSR] = cpsr;
-            updateRegMap(cpsr);
-
-            SCTLR sctlr = 0;
-            sctlr.nmfi = (bool)sctlr_rst.nmfi;
-            sctlr.v = (bool)sctlr_rst.v;
-            sctlr.u    = 1;
-            sctlr.rao1 = 1;
-            sctlr.rao2 = 1;
-            sctlr.rao3 = 1;
-            sctlr.rao4 = 1;
-            miscRegs[MISCREG_SCTLR] = sctlr;
-            miscRegs[MISCREG_SCTLR_RST] = sctlr_rst;
-
-
-            /*
-             * Technically this should be 0, but we don't support those
-             * settings.
-             */
-            CPACR cpacr = 0;
-            // Enable CP 10, 11
-            cpacr.cp10 = 0x3;
-            cpacr.cp11 = 0x3;
-            miscRegs[MISCREG_CPACR] = cpacr;
-
-            /* Start with an event in the mailbox */
-            miscRegs[MISCREG_SEV_MAILBOX] = 1;
-
-            /*
-             * Implemented = '5' from "M5",
-             * Variant = 0,
-             */
-            miscRegs[MISCREG_MIDR] =
-                (0x35 << 24) | //Implementor is '5' from "M5"
-                (0 << 20)    | //Variant
-                (0xf << 16)  | //Architecture from CPUID scheme
-                (0 << 4)     | //Primary part number
-                (0 << 0)     | //Revision
-                0;
-
-            // Separate Instruction and Data TLBs.
-            miscRegs[MISCREG_TLBTR] = 1;
-
-            MVFR0 mvfr0 = 0;
-            mvfr0.advSimdRegisters = 2;
-            mvfr0.singlePrecision = 2;
-            mvfr0.doublePrecision = 2;
-            mvfr0.vfpExceptionTrapping = 0;
-            mvfr0.divide = 1;
-            mvfr0.squareRoot = 1;
-            mvfr0.shortVectors = 1;
-            mvfr0.roundingModes = 1;
-            miscRegs[MISCREG_MVFR0] = mvfr0;
-
-            MVFR1 mvfr1 = 0;
-            mvfr1.flushToZero = 1;
-            mvfr1.defaultNaN = 1;
-            mvfr1.advSimdLoadStore = 1;
-            mvfr1.advSimdInteger = 1;
-            mvfr1.advSimdSinglePrecision = 1;
-            mvfr1.advSimdHalfPrecision = 1;
-            mvfr1.vfpHalfPrecision = 1;
-            miscRegs[MISCREG_MVFR1] = mvfr1;
-
-            miscRegs[MISCREG_MPIDR] = 0;
-
-            //XXX We need to initialize the rest of the state.
-        }
+        void clear();
 
         MiscReg readMiscRegNoEffect(int misc_reg);
-
         MiscReg readMiscReg(int misc_reg, ThreadContext *tc);
-
         void setMiscRegNoEffect(int misc_reg, const MiscReg &val);
-
         void setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc);
 
         int
@@ -214,6 +137,46 @@ namespace ArmISA
             return reg;
         }
 
+        int
+        flattenMiscIndex(int reg)
+        {
+            if (reg == MISCREG_SPSR) {
+                int spsr_idx = NUM_MISCREGS;
+                CPSR cpsr = miscRegs[MISCREG_CPSR];
+                switch (cpsr.mode) {
+                  case MODE_USER:
+                    warn("User mode does not have SPSR\n");
+                    spsr_idx = MISCREG_SPSR;
+                    break;
+                  case MODE_FIQ:
+                    spsr_idx = MISCREG_SPSR_FIQ;
+                    break;
+                  case MODE_IRQ:
+                    spsr_idx = MISCREG_SPSR_IRQ;
+                    break;
+                  case MODE_SVC:
+                    spsr_idx = MISCREG_SPSR_SVC;
+                    break;
+                  case MODE_MON:
+                    spsr_idx = MISCREG_SPSR_MON;
+                    break;
+                  case MODE_ABORT:
+                    spsr_idx = MISCREG_SPSR_ABT;
+                    break;
+                  case MODE_UNDEFINED:
+                    spsr_idx = MISCREG_SPSR_UND;
+                    break;
+                  default:
+                    warn("Trying to access SPSR in an invalid mode: %d\n",
+                         cpsr.mode);
+                    spsr_idx = MISCREG_SPSR;
+                    break;
+                }
+                return spsr_idx;
+            }
+            return reg;
+        }
+
         void serialize(EventManager *em, std::ostream &os)
         {}
         void unserialize(EventManager *em, Checkpoint *cp,