*/
#ifndef __ARCH_ARM_ISA_HH__
-#define __ARCH_MRM_ISA_HH__
+#define __ARCH_ARM_ISA_HH__
#include "arch/arm/registers.hh"
+#include "arch/arm/tlb.hh"
#include "arch/arm/types.hh"
class ThreadContext;
}
public:
- void clear()
- {
- memset(miscRegs, 0, sizeof(miscRegs));
- CPSR cpsr = 0;
- cpsr.mode = MODE_USER;
- miscRegs[MISCREG_CPSR] = cpsr;
- updateRegMap(cpsr);
-
- SCTLR sctlr = 0;
- sctlr.nmfi = 1;
- sctlr.rao1 = 1;
- sctlr.rao2 = 1;
- sctlr.rao3 = 1;
- sctlr.rao4 = 1;
- miscRegs[MISCREG_SCTLR] = sctlr;
-
- /*
- * Technically this should be 0, but we don't support those
- * settings.
- */
- CPACR cpacr = 0;
- // Enable CP 10, 11
- cpacr.cp10 = 0x3;
- cpacr.cp11 = 0x3;
- miscRegs[MISCREG_CPACR] = cpacr;
-
- /* One region, unified map. */
- miscRegs[MISCREG_MPUIR] = 0x100;
-
- /*
- * Implemented = '5' from "M5",
- * Variant = 0,
- */
- miscRegs[MISCREG_MIDR] =
- (0x35 << 24) | //Implementor is '5' from "M5"
- (0 << 20) | //Variant
- (0xf << 16) | //Architecture from CPUID scheme
- (0 << 4) | //Primary part number
- (0 << 0) | //Revision
- 0;
-
- //XXX We need to initialize the rest of the state.
- }
-
- MiscReg
- readMiscRegNoEffect(int misc_reg)
- {
- assert(misc_reg < NumMiscRegs);
- if (misc_reg == MISCREG_SPSR) {
- CPSR cpsr = miscRegs[MISCREG_CPSR];
- switch (cpsr.mode) {
- case MODE_USER:
- return miscRegs[MISCREG_SPSR];
- case MODE_FIQ:
- return miscRegs[MISCREG_SPSR_FIQ];
- case MODE_IRQ:
- return miscRegs[MISCREG_SPSR_IRQ];
- case MODE_SVC:
- return miscRegs[MISCREG_SPSR_SVC];
- case MODE_MON:
- return miscRegs[MISCREG_SPSR_MON];
- case MODE_ABORT:
- return miscRegs[MISCREG_SPSR_ABT];
- case MODE_UNDEFINED:
- return miscRegs[MISCREG_SPSR_UND];
- default:
- return miscRegs[MISCREG_SPSR];
- }
- }
- return miscRegs[misc_reg];
- }
-
- MiscReg
- readMiscReg(int misc_reg, ThreadContext *tc)
- {
- if (misc_reg == MISCREG_CPSR) {
- CPSR cpsr = miscRegs[misc_reg];
- Addr pc = tc->readPC();
- if (pc & (ULL(1) << PcJBitShift))
- cpsr.j = 1;
- else
- cpsr.j = 0;
- if (pc & (ULL(1) << PcTBitShift))
- cpsr.t = 1;
- else
- cpsr.t = 0;
- return cpsr;
- }
- if (misc_reg >= MISCREG_CP15_UNIMP_START &&
- misc_reg < MISCREG_CP15_END) {
- panic("Unimplemented CP15 register %s read.\n",
- miscRegName[misc_reg]);
- }
- switch (misc_reg) {
- case MISCREG_CLIDR:
- warn("The clidr register always reports 0 caches.\n");
- break;
- case MISCREG_CCSIDR:
- warn("The ccsidr register isn't implemented and "
- "always reads as 0.\n");
- break;
- }
- return readMiscRegNoEffect(misc_reg);
- }
-
- void
- setMiscRegNoEffect(int misc_reg, const MiscReg &val)
- {
- assert(misc_reg < NumMiscRegs);
- if (misc_reg == MISCREG_SPSR) {
- CPSR cpsr = miscRegs[MISCREG_CPSR];
- switch (cpsr.mode) {
- case MODE_USER:
- miscRegs[MISCREG_SPSR] = val;
- return;
- case MODE_FIQ:
- miscRegs[MISCREG_SPSR_FIQ] = val;
- return;
- case MODE_IRQ:
- miscRegs[MISCREG_SPSR_IRQ] = val;
- return;
- case MODE_SVC:
- miscRegs[MISCREG_SPSR_SVC] = val;
- return;
- case MODE_MON:
- miscRegs[MISCREG_SPSR_MON] = val;
- return;
- case MODE_ABORT:
- miscRegs[MISCREG_SPSR_ABT] = val;
- return;
- case MODE_UNDEFINED:
- miscRegs[MISCREG_SPSR_UND] = val;
- return;
- default:
- miscRegs[MISCREG_SPSR] = val;
- return;
- }
- }
- miscRegs[misc_reg] = val;
- }
+ void clear();
- void
- setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
- {
- MiscReg newVal = val;
- if (misc_reg == MISCREG_CPSR) {
- updateRegMap(val);
- CPSR cpsr = val;
- Addr npc = tc->readNextPC() & ~PcModeMask;
- if (cpsr.j)
- npc = npc | (ULL(1) << PcJBitShift);
- if (cpsr.t)
- npc = npc | (ULL(1) << PcTBitShift);
-
- tc->setNextPC(npc);
- }
- if (misc_reg >= MISCREG_CP15_UNIMP_START &&
- misc_reg < MISCREG_CP15_END) {
- panic("Unimplemented CP15 register %s wrote with %#x.\n",
- miscRegName[misc_reg], val);
- }
- switch (misc_reg) {
- case MISCREG_CPACR:
- {
- CPACR newCpacr = 0;
- CPACR valCpacr = val;
- newCpacr.cp10 = valCpacr.cp10;
- newCpacr.cp11 = valCpacr.cp11;
- if (newCpacr.cp10 != 0x3 || newCpacr.cp11 != 3) {
- panic("Disabling coprocessors isn't implemented.\n");
- }
- newVal = newCpacr;
- }
- break;
- case MISCREG_CSSELR:
- warn("The csselr register isn't implemented.\n");
- break;
- }
- return setMiscRegNoEffect(misc_reg, newVal);
- }
+ MiscReg readMiscRegNoEffect(int misc_reg);
+ MiscReg readMiscReg(int misc_reg, ThreadContext *tc);
+ void setMiscRegNoEffect(int misc_reg, const MiscReg &val);
+ void setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc);
int
flattenIntIndex(int reg)
return reg;
}
+ int
+ flattenMiscIndex(int reg)
+ {
+ if (reg == MISCREG_SPSR) {
+ int spsr_idx = NUM_MISCREGS;
+ CPSR cpsr = miscRegs[MISCREG_CPSR];
+ switch (cpsr.mode) {
+ case MODE_USER:
+ warn("User mode does not have SPSR\n");
+ spsr_idx = MISCREG_SPSR;
+ break;
+ case MODE_FIQ:
+ spsr_idx = MISCREG_SPSR_FIQ;
+ break;
+ case MODE_IRQ:
+ spsr_idx = MISCREG_SPSR_IRQ;
+ break;
+ case MODE_SVC:
+ spsr_idx = MISCREG_SPSR_SVC;
+ break;
+ case MODE_MON:
+ spsr_idx = MISCREG_SPSR_MON;
+ break;
+ case MODE_ABORT:
+ spsr_idx = MISCREG_SPSR_ABT;
+ break;
+ case MODE_UNDEFINED:
+ spsr_idx = MISCREG_SPSR_UND;
+ break;
+ default:
+ warn("Trying to access SPSR in an invalid mode: %d\n",
+ cpsr.mode);
+ spsr_idx = MISCREG_SPSR;
+ break;
+ }
+ return spsr_idx;
+ }
+ return reg;
+ }
+
void serialize(EventManager *em, std::ostream &os)
{}
void unserialize(EventManager *em, Checkpoint *cp,
ISA()
{
+ SCTLR sctlr;
+ sctlr = 0;
+ miscRegs[MISCREG_SCTLR_RST] = sctlr;
+
clear();
}
};
projects / gem5.git / blobdiff