stats: update stats for mmap() change.

[gem5.git] / src / arch / arm / isa.hh

diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh
index ae5ff21318449f297f887bfb037043e6bbae6a56..ab5c72e6a7c16469b903c464fa79337b7671af49 100644 (file)
--- a/src/arch/arm/isa.hh
+++ b/src/arch/arm/isa.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010, 2012-2014 ARM Limited
+ * Copyright (c) 2010, 2012-2015 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -49,8 +49,8 @@
 #include "arch/arm/tlb.hh"
 #include "arch/arm/types.hh"
 #include "debug/Checkpoint.hh"
-#include "dev/arm/generic_timer.hh"
 #include "sim/sim_object.hh"
+#include "enums/DecoderFlavour.hh"
 
 struct ArmISAParams;
 struct DummyArmISADeviceParams;
@@ -133,12 +133,18 @@ namespace ArmISA
         // Parent system
         ArmSystem *system;
 
+        // Micro Architecture
+        const Enums::DecoderFlavour _decoderFlavour;
+
         /** Dummy device for to handle non-existing ISA devices */
         DummyISADevice dummyDevice;
 
         // PMU belonging to this ISA
         BaseISADevice *pmu;
 
+        // Generic timer interface belonging to this ISA
+        std::unique_ptr<BaseISADevice> timer;
+
         // Cached copies of system-level properties
         bool haveSecurity;
         bool haveLPAE;
@@ -205,9 +211,7 @@ namespace ArmISA
             }
         }
 
-        ::GenericTimer::SystemCounter * getSystemCounter(ThreadContext *tc);
-        ::GenericTimer::ArchTimer * getArchTimer(ThreadContext *tc,
-                                                 int cpu_id);
+        BaseISADevice &getGenericTimer(ThreadContext *tc);
 
 
       private:
@@ -221,7 +225,7 @@ namespace ArmISA
             assert(!cpsr.width);
         }
 
-        void tlbiVA(ThreadContext *tc, MiscReg newVal, uint8_t asid,
+        void tlbiVA(ThreadContext *tc, MiscReg newVal, uint16_t asid,
                     bool secure_lookup, uint8_t target_el);
 
         void tlbiALL(ThreadContext *tc, bool secure_lookup, uint8_t target_el);
@@ -402,7 +406,7 @@ namespace ArmISA
             return flat_idx;
         }
 
-        void serialize(std::ostream &os)
+        void serialize(CheckpointOut &cp) const
         {
             DPRINTF(Checkpoint, "Serializing Arm Misc Registers\n");
             SERIALIZE_ARRAY(miscRegs, NumMiscRegs);
@@ -413,7 +417,7 @@ namespace ArmISA
             SERIALIZE_SCALAR(haveLargeAsid64);
             SERIALIZE_SCALAR(physAddrRange64);
         }
-        void unserialize(Checkpoint *cp, const std::string &section)
+        void unserialize(CheckpointIn &cp)
         {
             DPRINTF(Checkpoint, "Unserializing Arm Misc Registers\n");
             UNSERIALIZE_ARRAY(miscRegs, NumMiscRegs);
@@ -429,13 +433,7 @@ namespace ArmISA
 
         void startup(ThreadContext *tc) {}
 
-        /** Check if all CPUs have their caches enabled and if they do
-         * disable the bootAddrUncacheability flag because it's no longer
-         * needed.
-         * @s_idx the register number of the SCTLR that we are checking
-         * @tc Threadcontext to use to get access to the system and other cpus
-         */
-        void updateBootUncacheable(int sctlr_idx, ThreadContext *tc);
+        Enums::DecoderFlavour decoderFlavour() const { return _decoderFlavour; }
 
         /// Explicitly import the otherwise hidden startup
         using SimObject::startup;