stats: update stats for mmap() change.

[gem5.git] / src / arch / arm / isa.hh

diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh
index c72d5d50f17c0cea88d9c5e7421d6d0a29a507f7..ab5c72e6a7c16469b903c464fa79337b7671af49 100644 (file)
--- a/src/arch/arm/isa.hh
+++ b/src/arch/arm/isa.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010, 2012-2013 ARM Limited
+ * Copyright (c) 2010, 2012-2015 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -43,15 +43,17 @@
 #ifndef __ARCH_ARM_ISA_HH__
 #define __ARCH_ARM_ISA_HH__
 
+#include "arch/arm/isa_device.hh"
 #include "arch/arm/registers.hh"
 #include "arch/arm/system.hh"
 #include "arch/arm/tlb.hh"
 #include "arch/arm/types.hh"
 #include "debug/Checkpoint.hh"
-#include "dev/arm/generic_timer.hh"
 #include "sim/sim_object.hh"
+#include "enums/DecoderFlavour.hh"
 
 struct ArmISAParams;
+struct DummyArmISADeviceParams;
 class ThreadContext;
 class Checkpoint;
 class EventManager;
@@ -131,6 +133,18 @@ namespace ArmISA
         // Parent system
         ArmSystem *system;
 
+        // Micro Architecture
+        const Enums::DecoderFlavour _decoderFlavour;
+
+        /** Dummy device for to handle non-existing ISA devices */
+        DummyISADevice dummyDevice;
+
+        // PMU belonging to this ISA
+        BaseISADevice *pmu;
+
+        // Generic timer interface belonging to this ISA
+        std::unique_ptr<BaseISADevice> timer;
+
         // Cached copies of system-level properties
         bool haveSecurity;
         bool haveLPAE;
@@ -197,9 +211,7 @@ namespace ArmISA
             }
         }
 
-        ::GenericTimer::SystemCounter * getSystemCounter(ThreadContext *tc);
-        ::GenericTimer::ArchTimer * getArchTimer(ThreadContext *tc,
-                                                 int cpu_id);
+        BaseISADevice &getGenericTimer(ThreadContext *tc);
 
 
       private:
@@ -213,7 +225,7 @@ namespace ArmISA
             assert(!cpsr.width);
         }
 
-        void tlbiVA(ThreadContext *tc, MiscReg newVal, uint8_t asid,
+        void tlbiVA(ThreadContext *tc, MiscReg newVal, uint16_t asid,
                     bool secure_lookup, uint8_t target_el);
 
         void tlbiALL(ThreadContext *tc, bool secure_lookup, uint8_t target_el);
@@ -268,19 +280,21 @@ namespace ArmISA
         int
         flattenFloatIndex(int reg) const
         {
+            assert(reg >= 0);
             return reg;
         }
 
-        // dummy
         int
         flattenCCIndex(int reg) const
         {
+            assert(reg >= 0);
             return reg;
         }
 
         int
         flattenMiscIndex(int reg) const
         {
+            assert(reg >= 0);
             int flat_idx = reg;
 
             if (reg == MISCREG_SPSR) {
@@ -392,7 +406,7 @@ namespace ArmISA
             return flat_idx;
         }
 
-        void serialize(std::ostream &os)
+        void serialize(CheckpointOut &cp) const
         {
             DPRINTF(Checkpoint, "Serializing Arm Misc Registers\n");
             SERIALIZE_ARRAY(miscRegs, NumMiscRegs);
@@ -403,7 +417,7 @@ namespace ArmISA
             SERIALIZE_SCALAR(haveLargeAsid64);
             SERIALIZE_SCALAR(physAddrRange64);
         }
-        void unserialize(Checkpoint *cp, const std::string &section)
+        void unserialize(CheckpointIn &cp)
         {
             DPRINTF(Checkpoint, "Unserializing Arm Misc Registers\n");
             UNSERIALIZE_ARRAY(miscRegs, NumMiscRegs);
@@ -419,6 +433,8 @@ namespace ArmISA
 
         void startup(ThreadContext *tc) {}
 
+        Enums::DecoderFlavour decoderFlavour() const { return _decoderFlavour; }
+
         /// Explicitly import the otherwise hidden startup
         using SimObject::startup;