/*
- * Copyright (c) 2010 ARM Limited
+ * Copyright (c) 2010, 2012 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
#include "arch/arm/types.hh"
#include "base/types.hh"
+#include "cpu/static_inst_fwd.hh"
-namespace LittleEndianGuest {};
-
-#define TARGET_ARM
-
-class StaticInstPtr;
+namespace LittleEndianGuest {}
namespace ArmISA
{
const Addr USegBase = ULL(0x0);
const Addr USegEnd = ULL(0x7FFFFFFF);
- // Kernel Segment 0 - Unmapped
- const Addr KSeg0End = ULL(0x9FFFFFFF);
- const Addr KSeg0Base = ULL(0x80000000);
- const Addr KSeg0Mask = ULL(0x1FFFFFFF);
-
- // For loading... XXX This maybe could be USegEnd?? --ali
- const Addr LoadAddrMask = ULL(0xffffffffff);
-
const unsigned VABits = 32;
const unsigned PABits = 32; // Is this correct?
const Addr VAddrImplMask = (ULL(1) << VABits) - 1;
const Addr PAddrImplMask = (ULL(1) << PABits) - 1;
- // return a no-op instruction... used for instruction fetch faults
- const ExtMachInst NoopMachInst = 0x00000000;
-
- const int LogVMPageSize = 12; // 4K bytes
- const int VMPageSize = (1 << LogVMPageSize);
+ // Max. physical address range in bits supported by the architecture
+ const unsigned MaxPhysAddrRange = 48;
- const int BranchPredAddrShiftAmt = 2; // instructions are 4-byte aligned
+ // return a no-op instruction... used for instruction fetch faults
+ const ExtMachInst NoopMachInst = 0x01E320F000ULL;
const int MachineBytes = 4;
- const int WordBytes = 4;
- const int HalfwordBytes = 2;
- const int ByteBytes = 1;
const uint32_t HighVecs = 0xFFFF0000;
// Memory accesses cannot be unaligned
- const bool HasUnalignedMemAcc = false;
-};
+ const bool HasUnalignedMemAcc = true;
+
+ const bool CurThreadInfoImplemented = false;
+ const int CurThreadInfoReg = -1;
+
+ enum InterruptTypes
+ {
+ INT_RST,
+ INT_ABT,
+ INT_IRQ,
+ INT_FIQ,
+ INT_SEV, // Special interrupt for recieving SEV's
+ INT_VIRT_IRQ,
+ INT_VIRT_FIQ,
+ NumInterruptTypes
+ };
+} // namespace ArmISA
using namespace ArmISA;