/*
- * Copyright (c) 2010 ARM Limited
+ * Copyright (c) 2010, 2012 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
#include "arch/arm/types.hh"
#include "base/types.hh"
+#include "cpu/static_inst_fwd.hh"
-namespace LittleEndianGuest {};
-
-#define TARGET_ARM
-
-class StaticInstPtr;
+namespace LittleEndianGuest {}
namespace ArmISA
{
const Addr PAddrImplMask = (ULL(1) << PABits) - 1;
- // return a no-op instruction... used for instruction fetch faults
- const ExtMachInst NoopMachInst = 0x00000000;
-
- const int LogVMPageSize = 12; // 4K bytes
- const int VMPageSize = (1 << LogVMPageSize);
+ // Max. physical address range in bits supported by the architecture
+ const unsigned MaxPhysAddrRange = 48;
- // Shouldn't this be 1 because of Thumb?! Dynamic? --Ali
- const int BranchPredAddrShiftAmt = 2; // instructions are 4-byte aligned
+ // return a no-op instruction... used for instruction fetch faults
+ const ExtMachInst NoopMachInst = 0x01E320F000ULL;
const int MachineBytes = 4;
- const int WordBytes = 4;
- const int HalfwordBytes = 2;
- const int ByteBytes = 1;
const uint32_t HighVecs = 0xFFFF0000;
// Memory accesses cannot be unaligned
const bool HasUnalignedMemAcc = true;
+ const bool CurThreadInfoImplemented = false;
+ const int CurThreadInfoReg = -1;
+
enum InterruptTypes
{
INT_RST,
INT_ABT,
INT_IRQ,
INT_FIQ,
+ INT_SEV, // Special interrupt for recieving SEV's
+ INT_VIRT_IRQ,
+ INT_VIRT_FIQ,
NumInterruptTypes
};
-
- // These otherwise unused bits of the PC are used to select a mode
- // like the J and T bits of the CPSR.
- static const Addr PcJBitShift = 33;
- static const Addr PcTBitShift = 34;
- static const Addr PcModeMask = (ULL(1) << PcJBitShift) |
- (ULL(1) << PcTBitShift);
-};
+} // namespace ArmISA
using namespace ArmISA;