stats: update stats for mmap() change.

[gem5.git] / src / arch / arm / isa_traits.hh

diff --git a/src/arch/arm/isa_traits.hh b/src/arch/arm/isa_traits.hh
index c3cb622f42f4c01482fef7c84351dd5f8094bad0..8be2bf04ab325d7f3161fa6c7a46f2f8e232dc9e 100644 (file)
--- a/src/arch/arm/isa_traits.hh
+++ b/src/arch/arm/isa_traits.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010 ARM Limited
+ * Copyright (c) 2010, 2012 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -47,13 +47,10 @@
 
 #include "arch/arm/types.hh"
 #include "base/types.hh"
+#include "cpu/static_inst_fwd.hh"
 
 namespace LittleEndianGuest {}
 
-#define TARGET_ARM
-
-class StaticInstPtr;
-
 namespace ArmISA
 {
     using namespace LittleEndianGuest;
@@ -96,31 +93,31 @@ namespace ArmISA
 
     const Addr PAddrImplMask = (ULL(1) << PABits) - 1;
 
-    // return a no-op instruction... used for instruction fetch faults
-    const ExtMachInst NoopMachInst = 0xE320F000;
-
-    const int LogVMPageSize = 12;       // 4K bytes
-    const int VMPageSize = (1 << LogVMPageSize);
+    // Max. physical address range in bits supported by the architecture
+    const unsigned MaxPhysAddrRange = 48;
 
-    // Shouldn't this be 1 because of Thumb?! Dynamic? --Ali
-    const int BranchPredAddrShiftAmt = 2; // instructions are 4-byte aligned
+    // return a no-op instruction... used for instruction fetch faults
+    const ExtMachInst NoopMachInst = 0x01E320F000ULL;
 
     const int MachineBytes = 4;
-    const int WordBytes = 4;
-    const int HalfwordBytes = 2;
-    const int ByteBytes = 1;
 
     const uint32_t HighVecs = 0xFFFF0000;
 
     // Memory accesses cannot be unaligned
     const bool HasUnalignedMemAcc = true;
 
+    const bool CurThreadInfoImplemented = false;
+    const int CurThreadInfoReg = -1;
+
     enum InterruptTypes
     {
         INT_RST,
         INT_ABT,
         INT_IRQ,
         INT_FIQ,
+        INT_SEV, // Special interrupt for recieving SEV's
+        INT_VIRT_IRQ,
+        INT_VIRT_FIQ,
         NumInterruptTypes
     };
 } // namespace ArmISA