/*
+ * Copyright (c) 2010, 2012 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
* Copyright (c) 2003-2005 The Regents of The University of Michigan
* Copyright (c) 2007-2008 The Florida State University
* All rights reserved.
#define __ARCH_ARM_ISA_TRAITS_HH__
#include "arch/arm/types.hh"
-#include "sim/host.hh"
-
-namespace LittleEndianGuest {};
+#include "base/types.hh"
+#include "cpu/static_inst_fwd.hh"
-#define TARGET_ARM
-
-class StaticInstPtr;
+namespace LittleEndianGuest {}
namespace ArmISA
{
const Addr USegBase = ULL(0x0);
const Addr USegEnd = ULL(0x7FFFFFFF);
- // Kernel Segment 0 - Unmapped
- const Addr KSeg0End = ULL(0x9FFFFFFF);
- const Addr KSeg0Base = ULL(0x80000000);
- const Addr KSeg0Mask = ULL(0x1FFFFFFF);
-
- // For loading... XXX This maybe could be USegEnd?? --ali
- const Addr LoadAddrMask = ULL(0xffffffffff);
-
const unsigned VABits = 32;
const unsigned PABits = 32; // Is this correct?
const Addr VAddrImplMask = (ULL(1) << VABits) - 1;
const Addr PAddrImplMask = (ULL(1) << PABits) - 1;
- // return a no-op instruction... used for instruction fetch faults
- const ExtMachInst NoopMachInst = 0x00000000;
-
- // Constants Related to the number of registers
- const int NumIntArchRegs = 16;
- const int NumIntSpecialRegs = 19;
- const int NumFloatArchRegs = 16;
- const int NumFloatSpecialRegs = 5;
- const int NumControlRegs = 7;
- const int NumInternalProcRegs = 0;
-
- const int NumIntRegs = NumIntArchRegs + NumIntSpecialRegs;
- const int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs;
- const int NumMiscRegs = NumControlRegs;
+ // Max. physical address range in bits supported by the architecture
+ const unsigned MaxPhysAddrRange = 48;
- const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumMiscRegs;
-
- const int TotalDataRegs = NumIntRegs + NumFloatRegs;
-
- // Static instruction parameters
- const int MaxInstSrcRegs = 5;
- const int MaxInstDestRegs = 3;
-
- // semantically meaningful register indices
- const int ReturnValueReg = 0;
- const int ReturnValueReg1 = 1;
- const int ReturnValueReg2 = 2;
- const int ArgumentReg0 = 0;
- const int ArgumentReg1 = 1;
- const int ArgumentReg2 = 2;
- const int ArgumentReg3 = 3;
- const int FramePointerReg = 11;
- const int StackPointerReg = 13;
- const int ReturnAddressReg = 14;
- const int PCReg = 15;
-
- const int ZeroReg = NumIntArchRegs;
- const int AddrReg = ZeroReg + 1; // Used to generate address for uops
-
- const int SyscallNumReg = ReturnValueReg;
- const int SyscallPseudoReturnReg = ReturnValueReg;
- const int SyscallSuccessReg = ReturnValueReg;
-
- const int LogVMPageSize = 12; // 4K bytes
- const int VMPageSize = (1 << LogVMPageSize);
-
- const int BranchPredAddrShiftAmt = 2; // instructions are 4-byte aligned
+ // return a no-op instruction... used for instruction fetch faults
+ const ExtMachInst NoopMachInst = 0x01E320F000ULL;
const int MachineBytes = 4;
- const int WordBytes = 4;
- const int HalfwordBytes = 2;
- const int ByteBytes = 1;
-
- // These help enumerate all the registers for dependence tracking.
- const int FP_Base_DepTag = NumIntRegs;
- const int Ctrl_Base_DepTag = FP_Base_DepTag + NumFloatRegs;
-};
+
+ const uint32_t HighVecs = 0xFFFF0000;
+
+ // Memory accesses cannot be unaligned
+ const bool HasUnalignedMemAcc = true;
+
+ const bool CurThreadInfoImplemented = false;
+ const int CurThreadInfoReg = -1;
+
+ enum InterruptTypes
+ {
+ INT_RST,
+ INT_ABT,
+ INT_IRQ,
+ INT_FIQ,
+ INT_SEV, // Special interrupt for recieving SEV's
+ INT_VIRT_IRQ,
+ INT_VIRT_FIQ,
+ NumInterruptTypes
+ };
+} // namespace ArmISA
using namespace ArmISA;