stats: update stats for mmap() change.

[gem5.git] / src / arch / arm / isa_traits.hh

diff --git a/src/arch/arm/isa_traits.hh b/src/arch/arm/isa_traits.hh
index d81981ff7ef1b3e6aca0e87b78118a62e3360c21..8be2bf04ab325d7f3161fa6c7a46f2f8e232dc9e 100644 (file)
--- a/src/arch/arm/isa_traits.hh
+++ b/src/arch/arm/isa_traits.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010 ARM Limited
+ * Copyright (c) 2010, 2012 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -47,12 +47,9 @@
 
 #include "arch/arm/types.hh"
 #include "base/types.hh"
+#include "cpu/static_inst_fwd.hh"
 
-namespace LittleEndianGuest {};
-
-#define TARGET_ARM
-
-class StaticInstPtr;
+namespace LittleEndianGuest {}
 
 namespace ArmISA
 {
@@ -86,14 +83,6 @@ namespace ArmISA
     const Addr USegBase = ULL(0x0);
     const Addr USegEnd = ULL(0x7FFFFFFF);
 
-    // Kernel Segment 0 - Unmapped
-    const Addr KSeg0End = ULL(0x9FFFFFFF);
-    const Addr KSeg0Base =  ULL(0x80000000);
-    const Addr KSeg0Mask = ULL(0x1FFFFFFF);
-
-    // For loading... XXX This maybe could be USegEnd?? --ali
-    const Addr LoadAddrMask = ULL(0xffffffffff);
-
     const unsigned VABits = 32;
     const unsigned PABits = 32; // Is this correct?
     const Addr VAddrImplMask = (ULL(1) << VABits) - 1;
@@ -104,24 +93,21 @@ namespace ArmISA
 
     const Addr PAddrImplMask = (ULL(1) << PABits) - 1;
 
-    // return a no-op instruction... used for instruction fetch faults
-    const ExtMachInst NoopMachInst = 0x00000000;
+    // Max. physical address range in bits supported by the architecture
+    const unsigned MaxPhysAddrRange = 48;
 
-    const int LogVMPageSize = 12;      // 4K bytes
-    const int VMPageSize = (1 << LogVMPageSize);
-
-    // Shouldn't this be 1 because of Thumb?! Dynamic? --Ali
-    const int BranchPredAddrShiftAmt = 2; // instructions are 4-byte aligned
+    // return a no-op instruction... used for instruction fetch faults
+    const ExtMachInst NoopMachInst = 0x01E320F000ULL;
 
     const int MachineBytes = 4;
-    const int WordBytes = 4;
-    const int HalfwordBytes = 2;
-    const int ByteBytes = 1;
 
     const uint32_t HighVecs = 0xFFFF0000;
 
     // Memory accesses cannot be unaligned
-    const bool HasUnalignedMemAcc = false;
+    const bool HasUnalignedMemAcc = true;
+
+    const bool CurThreadInfoImplemented = false;
+    const int CurThreadInfoReg = -1;
 
     enum InterruptTypes
     {
@@ -129,16 +115,12 @@ namespace ArmISA
         INT_ABT,
         INT_IRQ,
         INT_FIQ,
+        INT_SEV, // Special interrupt for recieving SEV's
+        INT_VIRT_IRQ,
+        INT_VIRT_FIQ,
         NumInterruptTypes
     };
-
-    // These otherwise unused bits of the PC are used to select a mode
-    // like the J and T bits of the CPSR.
-    static const Addr PcJBitShift = 33;
-    static const Addr PcTBitShift = 34;
-    static const Addr PcModeMask = (ULL(1) << PcJBitShift) |
-                                   (ULL(1) << PcTBitShift);
-};
+} // namespace ArmISA
 
 using namespace ArmISA;