Mem: Reclaim some request flags used by MIPS for alignment checking.

[gem5.git] / src / arch / arm / isa_traits.hh

diff --git a/src/arch/arm/isa_traits.hh b/src/arch/arm/isa_traits.hh
index cf07699ce2e80e7eddf48b74656ea61142f5e451..8d3f0ffe3e7193854ec34b0194a7239ab2d005f2 100644 (file)
--- a/src/arch/arm/isa_traits.hh
+++ b/src/arch/arm/isa_traits.hh
@@ -1,4 +1,16 @@
 /*
+ * Copyright (c) 2010 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
  * Copyright (c) 2003-2005 The Regents of The University of Michigan
  * Copyright (c) 2007-2008 The Florida State University
  * All rights reserved.
@@ -34,7 +46,7 @@
 #define __ARCH_ARM_ISA_TRAITS_HH__
 
 #include "arch/arm/types.hh"
-#include "sim/host.hh"
+#include "base/types.hh"
 
 namespace LittleEndianGuest {};
 
@@ -74,14 +86,6 @@ namespace ArmISA
     const Addr USegBase = ULL(0x0);
     const Addr USegEnd = ULL(0x7FFFFFFF);
 
-    // Kernel Segment 0 - Unmapped
-    const Addr KSeg0End = ULL(0x9FFFFFFF);
-    const Addr KSeg0Base =  ULL(0x80000000);
-    const Addr KSeg0Mask = ULL(0x1FFFFFFF);
-
-    // For loading... XXX This maybe could be USegEnd?? --ali
-    const Addr LoadAddrMask = ULL(0xffffffffff);
-
     const unsigned VABits = 32;
     const unsigned PABits = 32; // Is this correct?
     const Addr VAddrImplMask = (ULL(1) << VABits) - 1;
@@ -95,49 +99,10 @@ namespace ArmISA
     // return a no-op instruction... used for instruction fetch faults
     const ExtMachInst NoopMachInst = 0x00000000;
 
-    // Constants Related to the number of registers
-    const int NumIntArchRegs = 16;
-    const int NumIntSpecialRegs = 19;
-    const int NumFloatArchRegs = 16;
-    const int NumFloatSpecialRegs = 5;
-    const int NumControlRegs = 7;
-    const int NumInternalProcRegs = 0;
-
-    const int NumIntRegs = NumIntArchRegs + NumIntSpecialRegs;
-    const int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs;
-    const int NumMiscRegs = NumControlRegs;
-
-    const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumMiscRegs;
-
-    const int TotalDataRegs = NumIntRegs + NumFloatRegs;
-
-    // Static instruction parameters
-    const int MaxInstSrcRegs = 5;
-    const int MaxInstDestRegs = 3;
-
-    // semantically meaningful register indices
-    const int ReturnValueReg = 0;
-    const int ReturnValueReg1 = 1;
-    const int ReturnValueReg2 = 2;
-    const int ArgumentReg0 = 0;
-    const int ArgumentReg1 = 1;
-    const int ArgumentReg2 = 2;
-    const int ArgumentReg3 = 3;
-    const int FramePointerReg = 11;
-    const int StackPointerReg = 13;
-    const int ReturnAddressReg = 14;
-    const int PCReg = 15;
-
-    const int ZeroReg = NumIntArchRegs;
-    const int AddrReg = ZeroReg + 1; // Used to generate address for uops
-
-    const int SyscallNumReg = ReturnValueReg;
-    const int SyscallPseudoReturnReg = ReturnValueReg;
-    const int SyscallSuccessReg = ReturnValueReg;
-
     const int LogVMPageSize = 12;      // 4K bytes
     const int VMPageSize = (1 << LogVMPageSize);
 
+    // Shouldn't this be 1 because of Thumb?! Dynamic? --Ali
     const int BranchPredAddrShiftAmt = 2; // instructions are 4-byte aligned
 
     const int MachineBytes = 4;
@@ -145,9 +110,28 @@ namespace ArmISA
     const int HalfwordBytes = 2;
     const int ByteBytes = 1;
 
-    // These help enumerate all the registers for dependence tracking.
-    const int FP_Base_DepTag = NumIntRegs;
-    const int Ctrl_Base_DepTag = FP_Base_DepTag + NumFloatRegs;
+    const uint32_t HighVecs = 0xFFFF0000;
+
+    // Memory accesses cannot be unaligned
+    const bool HasUnalignedMemAcc = true;
+
+    enum InterruptTypes
+    {
+        INT_RST,
+        INT_ABT,
+        INT_IRQ,
+        INT_FIQ,
+        NumInterruptTypes
+    };
+
+    // These otherwise unused bits of the PC are used to select a mode
+    // like the J and T bits of the CPSR.
+    static const Addr PcJBitShift = 33;
+    static const Addr PcJBit = ULL(1) << PcJBitShift;
+    static const Addr PcTBitShift = 34;
+    static const Addr PcTBit = ULL(1) << PcTBitShift;
+    static const Addr PcModeMask = (ULL(1) << PcJBitShift) |
+                                   (ULL(1) << PcTBitShift);
 };
 
 using namespace ArmISA;