/*
- * Copyright (c) 2010-2012 ARM Limited
+ * Copyright (c) 2010-2013 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
*
* Authors: Gabe Black
* Ali Saidi
+ * Giacomo Gabrielli
*/
#include "arch/arm/isa.hh"
#include "arch/arm/miscregs.hh"
#include "base/misc.hh"
+#include "cpu/thread_context.hh"
namespace ArmISA
{
{
switch(crn) {
case 0:
- switch (opc2) {
+ switch (opc1) {
case 0:
+ switch (opc2) {
+ case 0:
+ switch (crm) {
+ case 0:
+ return MISCREG_DBGDIDR;
+ case 1:
+ return MISCREG_DBGDSCRint;
+ }
+ break;
+ }
+ break;
+ case 7:
+ switch (opc2) {
+ case 0:
+ switch (crm) {
+ case 0:
+ return MISCREG_JIDR;
+ }
+ break;
+ }
+ break;
+ }
+ break;
+ case 1:
+ switch (opc1) {
+ case 6:
switch (crm) {
case 0:
- return MISCREG_DBGDIDR;
- case 1:
- return MISCREG_DBGDSCR_INT;
- default:
- warn("CP14 unimplemented crn[%d], opc1[%d], crm[%d], opc2[%d]",
- crn, opc1, crm, opc2);
- return NUM_MISCREGS;
- }
- default:
- warn("CP14 unimplemented crn[%d], opc1[%d], crm[%d], opc2[%d]",
- crn, opc1, crm, opc2);
- return NUM_MISCREGS;
+ switch (opc2) {
+ case 0:
+ return MISCREG_TEEHBR;
+ }
+ break;
+ }
+ break;
+ case 7:
+ switch (crm) {
+ case 0:
+ switch (opc2) {
+ case 0:
+ return MISCREG_JOSCR;
+ }
+ break;
+ }
+ break;
}
- default:
- warn("CP14 unimplemented crn[%d], opc1[%d], crm[%d], opc2[%d]",
- crn, opc1, crm, opc2);
- return NUM_MISCREGS;
+ break;
+ case 2:
+ switch (opc1) {
+ case 7:
+ switch (crm) {
+ case 0:
+ switch (opc2) {
+ case 0:
+ return MISCREG_JMCR;
+ }
+ break;
+ }
+ break;
+ }
+ break;
}
-
+ // If we get here then it must be a register that we haven't implemented
+ warn("CP14 unimplemented crn[%d], opc1[%d], crm[%d], opc2[%d]",
+ crn, opc1, crm, opc2);
+ return MISCREG_CP14_UNIMPL;
}
+using namespace std;
+
+bitset<NUM_MISCREG_INFOS> miscRegInfo[NUM_MISCREGS] = {
+ // MISCREG_CPSR
+ bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
+ // MISCREG_SPSR
+ bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
+ // MISCREG_SPSR_FIQ
+ bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
+ // MISCREG_SPSR_IRQ
+ bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
+ // MISCREG_SPSR_SVC
+ bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
+ // MISCREG_SPSR_MON
+ bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
+ // MISCREG_SPSR_ABT
+ bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
+ // MISCREG_SPSR_HYP
+ bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
+ // MISCREG_SPSR_UND
+ bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
+ // MISCREG_ELR_HYP
+ bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
+ // MISCREG_FPSID
+ bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
+ // MISCREG_FPSCR
+ bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
+ // MISCREG_MVFR1
+ bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
+ // MISCREG_MVFR0
+ bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
+ // MISCREG_FPEXC
+ bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
+
+ // Helper registers
+ // MISCREG_CPSR_MODE
+ bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
+ // MISCREG_CPSR_Q
+ bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
+ // MISCREG_FPSCR_Q
+ bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
+ // MISCREG_FPSCR_EXC
+ bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
+ // MISCREG_LOCKADDR
+ bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
+ // MISCREG_LOCKFLAG
+ bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
+ // MISCREG_PRRR_MAIR0
+ bitset<NUM_MISCREG_INFOS>(string("00000000000000011001")),
+ // MISCREG_PRRR_MAIR0_NS
+ bitset<NUM_MISCREG_INFOS>(string("00000000000000101001")),
+ // MISCREG_PRRR_MAIR0_S
+ bitset<NUM_MISCREG_INFOS>(string("00000000000000101001")),
+ // MISCREG_NMRR_MAIR1
+ bitset<NUM_MISCREG_INFOS>(string("00000000000000011001")),
+ // MISCREG_NMRR_MAIR1_NS
+ bitset<NUM_MISCREG_INFOS>(string("00000000000000101001")),
+ // MISCREG_NMRR_MAIR1_S
+ bitset<NUM_MISCREG_INFOS>(string("00000000000000101001")),
+ // MISCREG_PMXEVTYPER_PMCCFILTR
+ bitset<NUM_MISCREG_INFOS>(string("00000000000000001001")),
+ // MISCREG_SCTLR_RST
+ bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
+ // MISCREG_SEV_MAILBOX
+ bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
+
+ // AArch32 CP14 registers
+ // MISCREG_DBGDIDR
+ bitset<NUM_MISCREG_INFOS>(string("01011111111111000001")),
+ // MISCREG_DBGDSCRint
+ bitset<NUM_MISCREG_INFOS>(string("01011111111111000001")),
+ // MISCREG_DBGDCCINT
+ bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")),
+ // MISCREG_DBGDTRTXint
+ bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")),
+ // MISCREG_DBGDTRRXint
+ bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")),
+ // MISCREG_DBGWFAR
+ bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")),
+ // MISCREG_DBGVCR
+ bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")),
+ // MISCREG_DBGDTRRXext
+ bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")),
+ // MISCREG_DBGDSCRext
+ bitset<NUM_MISCREG_INFOS>(string("11111111111111000100")),
+ // MISCREG_DBGDTRTXext
+ bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")),
+ // MISCREG_DBGOSECCR
+ bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")),
+ // MISCREG_DBGBVR0
+ bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")),
+ // MISCREG_DBGBVR1
+ bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")),
+ // MISCREG_DBGBVR2
+ bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")),
+ // MISCREG_DBGBVR3
+ bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")),
+ // MISCREG_DBGBVR4
+ bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")),
+ // MISCREG_DBGBVR5
+ bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")),
+ // MISCREG_DBGBCR0
+ bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")),
+ // MISCREG_DBGBCR1
+ bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")),
+ // MISCREG_DBGBCR2
+ bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")),
+ // MISCREG_DBGBCR3
+ bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")),
+ // MISCREG_DBGBCR4
+ bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")),
+ // MISCREG_DBGBCR5
+ bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")),
+ // MISCREG_DBGWVR0
+ bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")),
+ // MISCREG_DBGWVR1
+ bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")),
+ // MISCREG_DBGWVR2
+ bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")),
+ // MISCREG_DBGWVR3
+ bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")),
+ // MISCREG_DBGWCR0
+ bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")),
+ // MISCREG_DBGWCR1
+ bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")),
+ // MISCREG_DBGWCR2
+ bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")),
+ // MISCREG_DBGWCR3
+ bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")),
+ // MISCREG_DBGDRAR
+ bitset<NUM_MISCREG_INFOS>(string("01011111111111000000")),
+ // MISCREG_DBGBXVR4
+ bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")),
+ // MISCREG_DBGBXVR5
+ bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")),
+ // MISCREG_DBGOSLAR
+ bitset<NUM_MISCREG_INFOS>(string("10101111111111000000")),
+ // MISCREG_DBGOSLSR
+ bitset<NUM_MISCREG_INFOS>(string("01011111111111000000")),
+ // MISCREG_DBGOSDLR
+ bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")),
+ // MISCREG_DBGPRCR
+ bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")),
+ // MISCREG_DBGDSAR
+ bitset<NUM_MISCREG_INFOS>(string("01011111111111000000")),
+ // MISCREG_DBGCLAIMSET
+ bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")),
+ // MISCREG_DBGCLAIMCLR
+ bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")),
+ // MISCREG_DBGAUTHSTATUS
+ bitset<NUM_MISCREG_INFOS>(string("01011111111111000000")),
+ // MISCREG_DBGDEVID2
+ bitset<NUM_MISCREG_INFOS>(string("01011111111111000000")),
+ // MISCREG_DBGDEVID1
+ bitset<NUM_MISCREG_INFOS>(string("01011111111111000000")),
+ // MISCREG_DBGDEVID0
+ bitset<NUM_MISCREG_INFOS>(string("01011111111111000000")),
+ // MISCREG_TEECR
+ bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")),
+ // MISCREG_JIDR
+ bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
+ // MISCREG_TEEHBR
+ bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
+ // MISCREG_JOSCR
+ bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
+ // MISCREG_JMCR
+ bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
+
+ // AArch32 CP15 registers
+ // MISCREG_MIDR
+ bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
+ // MISCREG_CTR
+ bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
+ // MISCREG_TCMTR
+ bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
+ // MISCREG_TLBTR
+ bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
+ // MISCREG_MPIDR
+ bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
+ // MISCREG_REVIDR
+ bitset<NUM_MISCREG_INFOS>(string("01010101010000000100")),
+ // MISCREG_ID_PFR0
+ bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
+ // MISCREG_ID_PFR1
+ bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
+ // MISCREG_ID_DFR0
+ bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
+ // MISCREG_ID_AFR0
+ bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
+ // MISCREG_ID_MMFR0
+ bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
+ // MISCREG_ID_MMFR1
+ bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
+ // MISCREG_ID_MMFR2
+ bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
+ // MISCREG_ID_MMFR3
+ bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
+ // MISCREG_ID_ISAR0
+ bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
+ // MISCREG_ID_ISAR1
+ bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
+ // MISCREG_ID_ISAR2
+ bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
+ // MISCREG_ID_ISAR3
+ bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
+ // MISCREG_ID_ISAR4
+ bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
+ // MISCREG_ID_ISAR5
+ bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
+ // MISCREG_CCSIDR
+ bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
+ // MISCREG_CLIDR
+ bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
+ // MISCREG_AIDR
+ bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
+ // MISCREG_CSSELR
+ bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")),
+ // MISCREG_CSSELR_NS
+ bitset<NUM_MISCREG_INFOS>(string("11001100110000100001")),
+ // MISCREG_CSSELR_S
+ bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")),
+ // MISCREG_VPIDR
+ bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")),
+ // MISCREG_VMPIDR
+ bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")),
+ // MISCREG_SCTLR
+ bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")),
+ // MISCREG_SCTLR_NS
+ bitset<NUM_MISCREG_INFOS>(string("11001100110000100001")),
+ // MISCREG_SCTLR_S
+ bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")),
+ // MISCREG_ACTLR
+ bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")),
+ // MISCREG_ACTLR_NS
+ bitset<NUM_MISCREG_INFOS>(string("11001100110000100001")),
+ // MISCREG_ACTLR_S
+ bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")),
+ // MISCREG_CPACR
+ bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
+ // MISCREG_SCR
+ bitset<NUM_MISCREG_INFOS>(string("11110011000000000001")),
+ // MISCREG_SDER
+ bitset<NUM_MISCREG_INFOS>(string("11110000000000000001")),
+ // MISCREG_NSACR
+ bitset<NUM_MISCREG_INFOS>(string("11110111010000000001")),
+ // MISCREG_HSCTLR
+ bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")),
+ // MISCREG_HACTLR
+ bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")),
+ // MISCREG_HCR
+ bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")),
+ // MISCREG_HDCR
+ bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")),
+ // MISCREG_HCPTR
+ bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")),
+ // MISCREG_HSTR
+ bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")),
+ // MISCREG_HACR
+ bitset<NUM_MISCREG_INFOS>(string("11001100000000000100")),
+ // MISCREG_TTBR0
+ bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")),
+ // MISCREG_TTBR0_NS
+ bitset<NUM_MISCREG_INFOS>(string("11001100110000100001")),
+ // MISCREG_TTBR0_S
+ bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")),
+ // MISCREG_TTBR1
+ bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")),
+ // MISCREG_TTBR1_NS
+ bitset<NUM_MISCREG_INFOS>(string("11001100110000100001")),
+ // MISCREG_TTBR1_S
+ bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")),
+ // MISCREG_TTBCR
+ bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")),
+ // MISCREG_TTBCR_NS
+ bitset<NUM_MISCREG_INFOS>(string("11001100110000100001")),
+ // MISCREG_TTBCR_S
+ bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")),
+ // MISCREG_HTCR
+ bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")),
+ // MISCREG_VTCR
+ bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")),
+ // MISCREG_DACR
+ bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")),
+ // MISCREG_DACR_NS
+ bitset<NUM_MISCREG_INFOS>(string("11001100110000100001")),
+ // MISCREG_DACR_S
+ bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")),
+ // MISCREG_DFSR
+ bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")),
+ // MISCREG_DFSR_NS
+ bitset<NUM_MISCREG_INFOS>(string("11001100110000100001")),
+ // MISCREG_DFSR_S
+ bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")),
+ // MISCREG_IFSR
+ bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")),
+ // MISCREG_IFSR_NS
+ bitset<NUM_MISCREG_INFOS>(string("11001100110000100001")),
+ // MISCREG_IFSR_S
+ bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")),
+ // MISCREG_ADFSR
+ bitset<NUM_MISCREG_INFOS>(string("00000000000000010100")),
+ // MISCREG_ADFSR_NS
+ bitset<NUM_MISCREG_INFOS>(string("11001100110000100100")),
+ // MISCREG_ADFSR_S
+ bitset<NUM_MISCREG_INFOS>(string("00110011000000100100")),
+ // MISCREG_AIFSR
+ bitset<NUM_MISCREG_INFOS>(string("00000000000000010100")),
+ // MISCREG_AIFSR_NS
+ bitset<NUM_MISCREG_INFOS>(string("11001100110000100100")),
+ // MISCREG_AIFSR_S
+ bitset<NUM_MISCREG_INFOS>(string("00110011000000100100")),
+ // MISCREG_HADFSR
+ bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")),
+ // MISCREG_HAIFSR
+ bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")),
+ // MISCREG_HSR
+ bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")),
+ // MISCREG_DFAR
+ bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")),
+ // MISCREG_DFAR_NS
+ bitset<NUM_MISCREG_INFOS>(string("11001100110000100001")),
+ // MISCREG_DFAR_S
+ bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")),
+ // MISCREG_IFAR
+ bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")),
+ // MISCREG_IFAR_NS
+ bitset<NUM_MISCREG_INFOS>(string("11001100110000100001")),
+ // MISCREG_IFAR_S
+ bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")),
+ // MISCREG_HDFAR
+ bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")),
+ // MISCREG_HIFAR
+ bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")),
+ // MISCREG_HPFAR
+ bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")),
+ // MISCREG_ICIALLUIS
+ bitset<NUM_MISCREG_INFOS>(string("10101010100000000100")),
+ // MISCREG_BPIALLIS
+ bitset<NUM_MISCREG_INFOS>(string("10101010100000000100")),
+ // MISCREG_PAR
+ bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")),
+ // MISCREG_PAR_NS
+ bitset<NUM_MISCREG_INFOS>(string("11001100110000100001")),
+ // MISCREG_PAR_S
+ bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")),
+ // MISCREG_ICIALLU
+ bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")),
+ // MISCREG_ICIMVAU
+ bitset<NUM_MISCREG_INFOS>(string("10101010100000000100")),
+ // MISCREG_CP15ISB
+ bitset<NUM_MISCREG_INFOS>(string("10101010101010000001")),
+ // MISCREG_BPIALL
+ bitset<NUM_MISCREG_INFOS>(string("10101010100000000100")),
+ // MISCREG_BPIMVA
+ bitset<NUM_MISCREG_INFOS>(string("10101010100000000100")),
+ // MISCREG_DCIMVAC
+ bitset<NUM_MISCREG_INFOS>(string("10101010100000000100")),
+ // MISCREG_DCISW
+ bitset<NUM_MISCREG_INFOS>(string("10101010100000000100")),
+ // MISCREG_ATS1CPR
+ bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")),
+ // MISCREG_ATS1CPW
+ bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")),
+ // MISCREG_ATS1CUR
+ bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")),
+ // MISCREG_ATS1CUW
+ bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")),
+ // MISCREG_ATS12NSOPR
+ bitset<NUM_MISCREG_INFOS>(string("10101010000000000001")),
+ // MISCREG_ATS12NSOPW
+ bitset<NUM_MISCREG_INFOS>(string("10101010000000000001")),
+ // MISCREG_ATS12NSOUR
+ bitset<NUM_MISCREG_INFOS>(string("10101010000000000001")),
+ // MISCREG_ATS12NSOUW
+ bitset<NUM_MISCREG_INFOS>(string("10101010000000000001")),
+ // MISCREG_DCCMVAC
+ bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")),
+ // MISCREG_DCCSW
+ bitset<NUM_MISCREG_INFOS>(string("10101010100000000100")),
+ // MISCREG_CP15DSB
+ bitset<NUM_MISCREG_INFOS>(string("10101010101010000001")),
+ // MISCREG_CP15DMB
+ bitset<NUM_MISCREG_INFOS>(string("10101010101010000001")),
+ // MISCREG_DCCMVAU
+ bitset<NUM_MISCREG_INFOS>(string("10101010100000000100")),
+ // MISCREG_DCCIMVAC
+ bitset<NUM_MISCREG_INFOS>(string("10101010100000000100")),
+ // MISCREG_DCCISW
+ bitset<NUM_MISCREG_INFOS>(string("10101010100000000100")),
+ // MISCREG_ATS1HR
+ bitset<NUM_MISCREG_INFOS>(string("10001000000000000001")),
+ // MISCREG_ATS1HW
+ bitset<NUM_MISCREG_INFOS>(string("10001000000000000001")),
+ // MISCREG_TLBIALLIS
+ bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")),
+ // MISCREG_TLBIMVAIS
+ bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")),
+ // MISCREG_TLBIASIDIS
+ bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")),
+ // MISCREG_TLBIMVAAIS
+ bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")),
+ // MISCREG_TLBIMVALIS
+ bitset<NUM_MISCREG_INFOS>(string("10101010100000000000")),
+ // MISCREG_TLBIMVAALIS
+ bitset<NUM_MISCREG_INFOS>(string("10101010100000000000")),
+ // MISCREG_ITLBIALL
+ bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")),
+ // MISCREG_ITLBIMVA
+ bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")),
+ // MISCREG_ITLBIASID
+ bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")),
+ // MISCREG_DTLBIALL
+ bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")),
+ // MISCREG_DTLBIMVA
+ bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")),
+ // MISCREG_DTLBIASID
+ bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")),
+ // MISCREG_TLBIALL
+ bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")),
+ // MISCREG_TLBIMVA
+ bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")),
+ // MISCREG_TLBIASID
+ bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")),
+ // MISCREG_TLBIMVAA
+ bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")),
+ // MISCREG_TLBIMVAL
+ bitset<NUM_MISCREG_INFOS>(string("10101010100000000000")),
+ // MISCREG_TLBIMVAAL
+ bitset<NUM_MISCREG_INFOS>(string("10101010100000000000")),
+ // MISCREG_TLBIIPAS2IS
+ bitset<NUM_MISCREG_INFOS>(string("10001000000000000000")),
+ // MISCREG_TLBIIPAS2LIS
+ bitset<NUM_MISCREG_INFOS>(string("10001000000000000000")),
+ // MISCREG_TLBIALLHIS
+ bitset<NUM_MISCREG_INFOS>(string("10001000000000000001")),
+ // MISCREG_TLBIMVAHIS
+ bitset<NUM_MISCREG_INFOS>(string("10001000000000000001")),
+ // MISCREG_TLBIALLNSNHIS
+ bitset<NUM_MISCREG_INFOS>(string("10001000000000000001")),
+ // MISCREG_TLBIMVALHIS
+ bitset<NUM_MISCREG_INFOS>(string("10001000000000000000")),
+ // MISCREG_TLBIIPAS2
+ bitset<NUM_MISCREG_INFOS>(string("10001000000000000000")),
+ // MISCREG_TLBIIPAS2L
+ bitset<NUM_MISCREG_INFOS>(string("10001000000000000000")),
+ // MISCREG_TLBIALLH
+ bitset<NUM_MISCREG_INFOS>(string("10001000000000000001")),
+ // MISCREG_TLBIMVAH
+ bitset<NUM_MISCREG_INFOS>(string("10001000000000000001")),
+ // MISCREG_TLBIALLNSNH
+ bitset<NUM_MISCREG_INFOS>(string("10001000000000000001")),
+ // MISCREG_TLBIMVALH
+ bitset<NUM_MISCREG_INFOS>(string("10001000000000000000")),
+ // MISCREG_PMCR
+ bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
+ // MISCREG_PMCNTENSET
+ bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
+ // MISCREG_PMCNTENCLR
+ bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
+ // MISCREG_PMOVSR
+ bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
+ // MISCREG_PMSWINC
+ bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
+ // MISCREG_PMSELR
+ bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
+ // MISCREG_PMCEID0
+ bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
+ // MISCREG_PMCEID1
+ bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
+ // MISCREG_PMCCNTR
+ bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
+ // MISCREG_PMXEVTYPER
+ bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
+ // MISCREG_PMCCFILTR
+ bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
+ // MISCREG_PMXEVCNTR
+ bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
+ // MISCREG_PMUSERENR
+ bitset<NUM_MISCREG_INFOS>(string("11111111110101000001")),
+ // MISCREG_PMINTENSET
+ bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
+ // MISCREG_PMINTENCLR
+ bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
+ // MISCREG_PMOVSSET
+ bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")),
+ // MISCREG_L2CTLR
+ bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
+ // MISCREG_L2ECTLR
+ bitset<NUM_MISCREG_INFOS>(string("11111111110000000000")),
+ // MISCREG_PRRR
+ bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")),
+ // MISCREG_PRRR_NS
+ bitset<NUM_MISCREG_INFOS>(string("11001100110000100001")),
+ // MISCREG_PRRR_S
+ bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")),
+ // MISCREG_MAIR0
+ bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")),
+ // MISCREG_MAIR0_NS
+ bitset<NUM_MISCREG_INFOS>(string("11001100110000100001")),
+ // MISCREG_MAIR0_S
+ bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")),
+ // MISCREG_NMRR
+ bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")),
+ // MISCREG_NMRR_NS
+ bitset<NUM_MISCREG_INFOS>(string("11001100110000100001")),
+ // MISCREG_NMRR_S
+ bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")),
+ // MISCREG_MAIR1
+ bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")),
+ // MISCREG_MAIR1_NS
+ bitset<NUM_MISCREG_INFOS>(string("11001100110000100001")),
+ // MISCREG_MAIR1_S
+ bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")),
+ // MISCREG_AMAIR0
+ bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")),
+ // MISCREG_AMAIR0_NS
+ bitset<NUM_MISCREG_INFOS>(string("11001100110000100001")),
+ // MISCREG_AMAIR0_S
+ bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")),
+ // MISCREG_AMAIR1
+ bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")),
+ // MISCREG_AMAIR1_NS
+ bitset<NUM_MISCREG_INFOS>(string("11001100110000100001")),
+ // MISCREG_AMAIR1_S
+ bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")),
+ // MISCREG_HMAIR0
+ bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")),
+ // MISCREG_HMAIR1
+ bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")),
+ // MISCREG_HAMAIR0
+ bitset<NUM_MISCREG_INFOS>(string("11001100000000000100")),
+ // MISCREG_HAMAIR1
+ bitset<NUM_MISCREG_INFOS>(string("11001100000000000100")),
+ // MISCREG_VBAR
+ bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")),
+ // MISCREG_VBAR_NS
+ bitset<NUM_MISCREG_INFOS>(string("11001100110000100001")),
+ // MISCREG_VBAR_S
+ bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")),
+ // MISCREG_MVBAR
+ bitset<NUM_MISCREG_INFOS>(string("11110011000000000001")),
+ // MISCREG_RMR
+ bitset<NUM_MISCREG_INFOS>(string("11110011000000000000")),
+ // MISCREG_ISR
+ bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
+ // MISCREG_HVBAR
+ bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")),
+ // MISCREG_FCSEIDR
+ bitset<NUM_MISCREG_INFOS>(string("11111111110000000100")),
+ // MISCREG_CONTEXTIDR
+ bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")),
+ // MISCREG_CONTEXTIDR_NS
+ bitset<NUM_MISCREG_INFOS>(string("11001100110000100001")),
+ // MISCREG_CONTEXTIDR_S
+ bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")),
+ // MISCREG_TPIDRURW
+ bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")),
+ // MISCREG_TPIDRURW_NS
+ bitset<NUM_MISCREG_INFOS>(string("11001100111111100001")),
+ // MISCREG_TPIDRURW_S
+ bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")),
+ // MISCREG_TPIDRURO
+ bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")),
+ // MISCREG_TPIDRURO_NS
+ bitset<NUM_MISCREG_INFOS>(string("11001100110101100001")),
+ // MISCREG_TPIDRURO_S
+ bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")),
+ // MISCREG_TPIDRPRW
+ bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")),
+ // MISCREG_TPIDRPRW_NS
+ bitset<NUM_MISCREG_INFOS>(string("11001100110000100001")),
+ // MISCREG_TPIDRPRW_S
+ bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")),
+ // MISCREG_HTPIDR
+ bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")),
+ // MISCREG_CNTFRQ
+ bitset<NUM_MISCREG_INFOS>(string("11110101010101000011")),
+ // MISCREG_CNTKCTL
+ bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
+ // MISCREG_CNTP_TVAL
+ bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")),
+ // MISCREG_CNTP_TVAL_NS
+ bitset<NUM_MISCREG_INFOS>(string("11001100111111100001")),
+ // MISCREG_CNTP_TVAL_S
+ bitset<NUM_MISCREG_INFOS>(string("00110011001111100000")),
+ // MISCREG_CNTP_CTL
+ bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")),
+ // MISCREG_CNTP_CTL_NS
+ bitset<NUM_MISCREG_INFOS>(string("11001100111111100001")),
+ // MISCREG_CNTP_CTL_S
+ bitset<NUM_MISCREG_INFOS>(string("00110011001111100000")),
+ // MISCREG_CNTV_TVAL
+ bitset<NUM_MISCREG_INFOS>(string("01111000000000000000")),
+ // MISCREG_CNTV_CTL
+ bitset<NUM_MISCREG_INFOS>(string("01111000000000000000")),
+ // MISCREG_CNTHCTL
+ bitset<NUM_MISCREG_INFOS>(string("01001000000000000000")),
+ // MISCREG_CNTHP_TVAL
+ bitset<NUM_MISCREG_INFOS>(string("01001000000000000000")),
+ // MISCREG_CNTHP_CTL
+ bitset<NUM_MISCREG_INFOS>(string("01001000000000000000")),
+ // MISCREG_IL1DATA0
+ bitset<NUM_MISCREG_INFOS>(string("11111111110000000000")),
+ // MISCREG_IL1DATA1
+ bitset<NUM_MISCREG_INFOS>(string("11111111110000000000")),
+ // MISCREG_IL1DATA2
+ bitset<NUM_MISCREG_INFOS>(string("11111111110000000000")),
+ // MISCREG_IL1DATA3
+ bitset<NUM_MISCREG_INFOS>(string("11111111110000000000")),
+ // MISCREG_DL1DATA0
+ bitset<NUM_MISCREG_INFOS>(string("11111111110000000000")),
+ // MISCREG_DL1DATA1
+ bitset<NUM_MISCREG_INFOS>(string("11111111110000000000")),
+ // MISCREG_DL1DATA2
+ bitset<NUM_MISCREG_INFOS>(string("11111111110000000000")),
+ // MISCREG_DL1DATA3
+ bitset<NUM_MISCREG_INFOS>(string("11111111110000000000")),
+ // MISCREG_DL1DATA4
+ bitset<NUM_MISCREG_INFOS>(string("11111111110000000000")),
+ // MISCREG_RAMINDEX
+ bitset<NUM_MISCREG_INFOS>(string("10101010100000000000")),
+ // MISCREG_L2ACTLR
+ bitset<NUM_MISCREG_INFOS>(string("11111111110000000000")),
+ // MISCREG_CBAR
+ bitset<NUM_MISCREG_INFOS>(string("01010101010000000000")),
+ // MISCREG_HTTBR
+ bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")),
+ // MISCREG_VTTBR
+ bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")),
+ // MISCREG_CNTPCT
+ bitset<NUM_MISCREG_INFOS>(string("01010101010101000001")),
+ // MISCREG_CNTVCT
+ bitset<NUM_MISCREG_INFOS>(string("01010101010101000011")),
+ // MISCREG_CNTP_CVAL
+ bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")),
+ // MISCREG_CNTP_CVAL_NS
+ bitset<NUM_MISCREG_INFOS>(string("11001100111111100001")),
+ // MISCREG_CNTP_CVAL_S
+ bitset<NUM_MISCREG_INFOS>(string("00110011001111100000")),
+ // MISCREG_CNTV_CVAL
+ bitset<NUM_MISCREG_INFOS>(string("01111000000000000000")),
+ // MISCREG_CNTVOFF
+ bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")),
+ // MISCREG_CNTHP_CVAL
+ bitset<NUM_MISCREG_INFOS>(string("01001000000000000000")),
+ // MISCREG_CPUMERRSR
+ bitset<NUM_MISCREG_INFOS>(string("11111111110000000000")),
+ // MISCREG_L2MERRSR
+ bitset<NUM_MISCREG_INFOS>(string("11111111110000000100")),
+
+ // AArch64 registers (Op0=2)
+ // MISCREG_MDCCINT_EL1
+ bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
+ // MISCREG_OSDTRRX_EL1
+ bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
+ // MISCREG_MDSCR_EL1
+ bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
+ // MISCREG_OSDTRTX_EL1
+ bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
+ // MISCREG_OSECCR_EL1
+ bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
+ // MISCREG_DBGBVR0_EL1
+ bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
+ // MISCREG_DBGBVR1_EL1
+ bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
+ // MISCREG_DBGBVR2_EL1
+ bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
+ // MISCREG_DBGBVR3_EL1
+ bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
+ // MISCREG_DBGBVR4_EL1
+ bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
+ // MISCREG_DBGBVR5_EL1
+ bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
+ // MISCREG_DBGBCR0_EL1
+ bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
+ // MISCREG_DBGBCR1_EL1
+ bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
+ // MISCREG_DBGBCR2_EL1
+ bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
+ // MISCREG_DBGBCR3_EL1
+ bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
+ // MISCREG_DBGBCR4_EL1
+ bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
+ // MISCREG_DBGBCR5_EL1
+ bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
+ // MISCREG_DBGWVR0_EL1
+ bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
+ // MISCREG_DBGWVR1_EL1
+ bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
+ // MISCREG_DBGWVR2_EL1
+ bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
+ // MISCREG_DBGWVR3_EL1
+ bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
+ // MISCREG_DBGWCR0_EL1
+ bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
+ // MISCREG_DBGWCR1_EL1
+ bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
+ // MISCREG_DBGWCR2_EL1
+ bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
+ // MISCREG_DBGWCR3_EL1
+ bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
+ // MISCREG_MDCCSR_EL0
+ bitset<NUM_MISCREG_INFOS>(string("01011111111111000001")),
+ // MISCREG_MDDTR_EL0
+ bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
+ // MISCREG_MDDTRTX_EL0
+ bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
+ // MISCREG_MDDTRRX_EL0
+ bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
+ // MISCREG_DBGVCR32_EL2
+ bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
+ // MISCREG_MDRAR_EL1
+ bitset<NUM_MISCREG_INFOS>(string("01011111111111000001")),
+ // MISCREG_OSLAR_EL1
+ bitset<NUM_MISCREG_INFOS>(string("10101111111111000001")),
+ // MISCREG_OSLSR_EL1
+ bitset<NUM_MISCREG_INFOS>(string("01011111111111000001")),
+ // MISCREG_OSDLR_EL1
+ bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
+ // MISCREG_DBGPRCR_EL1
+ bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
+ // MISCREG_DBGCLAIMSET_EL1
+ bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
+ // MISCREG_DBGCLAIMCLR_EL1
+ bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
+ // MISCREG_DBGAUTHSTATUS_EL1
+ bitset<NUM_MISCREG_INFOS>(string("01011111111111000001")),
+ // MISCREG_TEECR32_EL1
+ bitset<NUM_MISCREG_INFOS>(string("00000000000000000001")),
+ // MISCREG_TEEHBR32_EL1
+ bitset<NUM_MISCREG_INFOS>(string("00000000000000000001")),
+
+ // AArch64 registers (Op0=1,3)
+ // MISCREG_MIDR_EL1
+ bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
+ // MISCREG_MPIDR_EL1
+ bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
+ // MISCREG_REVIDR_EL1
+ bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
+ // MISCREG_ID_PFR0_EL1
+ bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
+ // MISCREG_ID_PFR1_EL1
+ bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
+ // MISCREG_ID_DFR0_EL1
+ bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
+ // MISCREG_ID_AFR0_EL1
+ bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
+ // MISCREG_ID_MMFR0_EL1
+ bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
+ // MISCREG_ID_MMFR1_EL1
+ bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
+ // MISCREG_ID_MMFR2_EL1
+ bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
+ // MISCREG_ID_MMFR3_EL1
+ bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
+ // MISCREG_ID_ISAR0_EL1
+ bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
+ // MISCREG_ID_ISAR1_EL1
+ bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
+ // MISCREG_ID_ISAR2_EL1
+ bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
+ // MISCREG_ID_ISAR3_EL1
+ bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
+ // MISCREG_ID_ISAR4_EL1
+ bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
+ // MISCREG_ID_ISAR5_EL1
+ bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
+ // MISCREG_MVFR0_EL1
+ bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
+ // MISCREG_MVFR1_EL1
+ bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
+ // MISCREG_MVFR2_EL1
+ bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
+ // MISCREG_ID_AA64PFR0_EL1
+ bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
+ // MISCREG_ID_AA64PFR1_EL1
+ bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
+ // MISCREG_ID_AA64DFR0_EL1
+ bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
+ // MISCREG_ID_AA64DFR1_EL1
+ bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
+ // MISCREG_ID_AA64AFR0_EL1
+ bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
+ // MISCREG_ID_AA64AFR1_EL1
+ bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
+ // MISCREG_ID_AA64ISAR0_EL1
+ bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
+ // MISCREG_ID_AA64ISAR1_EL1
+ bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
+ // MISCREG_ID_AA64MMFR0_EL1
+ bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
+ // MISCREG_ID_AA64MMFR1_EL1
+ bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
+ // MISCREG_CCSIDR_EL1
+ bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
+ // MISCREG_CLIDR_EL1
+ bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
+ // MISCREG_AIDR_EL1
+ bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
+ // MISCREG_CSSELR_EL1
+ bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
+ // MISCREG_CTR_EL0
+ bitset<NUM_MISCREG_INFOS>(string("01010101010101000001")),
+ // MISCREG_DCZID_EL0
+ bitset<NUM_MISCREG_INFOS>(string("01010101010101000001")),
+ // MISCREG_VPIDR_EL2
+ bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")),
+ // MISCREG_VMPIDR_EL2
+ bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")),
+ // MISCREG_SCTLR_EL1
+ bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
+ // MISCREG_ACTLR_EL1
+ bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
+ // MISCREG_CPACR_EL1
+ bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
+ // MISCREG_SCTLR_EL2
+ bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")),
+ // MISCREG_ACTLR_EL2
+ bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")),
+ // MISCREG_HCR_EL2
+ bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")),
+ // MISCREG_MDCR_EL2
+ bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")),
+ // MISCREG_CPTR_EL2
+ bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")),
+ // MISCREG_HSTR_EL2
+ bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")),
+ // MISCREG_HACR_EL2
+ bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")),
+ // MISCREG_SCTLR_EL3
+ bitset<NUM_MISCREG_INFOS>(string("11110000000000000001")),
+ // MISCREG_ACTLR_EL3
+ bitset<NUM_MISCREG_INFOS>(string("11110000000000000001")),
+ // MISCREG_SCR_EL3
+ bitset<NUM_MISCREG_INFOS>(string("11110000000000000001")),
+ // MISCREG_SDER32_EL3
+ bitset<NUM_MISCREG_INFOS>(string("11110000000000000001")),
+ // MISCREG_CPTR_EL3
+ bitset<NUM_MISCREG_INFOS>(string("11110000000000000001")),
+ // MISCREG_MDCR_EL3
+ bitset<NUM_MISCREG_INFOS>(string("11110000000000000001")),
+ // MISCREG_TTBR0_EL1
+ bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
+ // MISCREG_TTBR1_EL1
+ bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
+ // MISCREG_TCR_EL1
+ bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
+ // MISCREG_TTBR0_EL2
+ bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")),
+ // MISCREG_TCR_EL2
+ bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")),
+ // MISCREG_VTTBR_EL2
+ bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")),
+ // MISCREG_VTCR_EL2
+ bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")),
+ // MISCREG_TTBR0_EL3
+ bitset<NUM_MISCREG_INFOS>(string("11110000000000000001")),
+ // MISCREG_TCR_EL3
+ bitset<NUM_MISCREG_INFOS>(string("11110000000000000001")),
+ // MISCREG_DACR32_EL2
+ bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")),
+ // MISCREG_SPSR_EL1
+ bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
+ // MISCREG_ELR_EL1
+ bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
+ // MISCREG_SP_EL0
+ bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
+ // MISCREG_SPSEL
+ bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
+ // MISCREG_CURRENTEL
+ bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
+ // MISCREG_NZCV
+ bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
+ // MISCREG_DAIF
+ bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
+ // MISCREG_FPCR
+ bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
+ // MISCREG_FPSR
+ bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
+ // MISCREG_DSPSR_EL0
+ bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
+ // MISCREG_DLR_EL0
+ bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
+ // MISCREG_SPSR_EL2
+ bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")),
+ // MISCREG_ELR_EL2
+ bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")),
+ // MISCREG_SP_EL1
+ bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")),
+ // MISCREG_SPSR_IRQ_AA64
+ bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")),
+ // MISCREG_SPSR_ABT_AA64
+ bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")),
+ // MISCREG_SPSR_UND_AA64
+ bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")),
+ // MISCREG_SPSR_FIQ_AA64
+ bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")),
+ // MISCREG_SPSR_EL3
+ bitset<NUM_MISCREG_INFOS>(string("11110000000000000001")),
+ // MISCREG_ELR_EL3
+ bitset<NUM_MISCREG_INFOS>(string("11110000000000000001")),
+ // MISCREG_SP_EL2
+ bitset<NUM_MISCREG_INFOS>(string("11110000000000000001")),
+ // MISCREG_AFSR0_EL1
+ bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
+ // MISCREG_AFSR1_EL1
+ bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
+ // MISCREG_ESR_EL1
+ bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
+ // MISCREG_IFSR32_EL2
+ bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")),
+ // MISCREG_AFSR0_EL2
+ bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")),
+ // MISCREG_AFSR1_EL2
+ bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")),
+ // MISCREG_ESR_EL2
+ bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")),
+ // MISCREG_FPEXC32_EL2
+ bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")),
+ // MISCREG_AFSR0_EL3
+ bitset<NUM_MISCREG_INFOS>(string("11110000000000000001")),
+ // MISCREG_AFSR1_EL3
+ bitset<NUM_MISCREG_INFOS>(string("11110000000000000001")),
+ // MISCREG_ESR_EL3
+ bitset<NUM_MISCREG_INFOS>(string("11110000000000000001")),
+ // MISCREG_FAR_EL1
+ bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
+ // MISCREG_FAR_EL2
+ bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")),
+ // MISCREG_HPFAR_EL2
+ bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")),
+ // MISCREG_FAR_EL3
+ bitset<NUM_MISCREG_INFOS>(string("11110000000000000001")),
+ // MISCREG_IC_IALLUIS
+ bitset<NUM_MISCREG_INFOS>(string("10101010100000000101")),
+ // MISCREG_PAR_EL1
+ bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
+ // MISCREG_IC_IALLU
+ bitset<NUM_MISCREG_INFOS>(string("10101010100000000101")),
+ // MISCREG_DC_IVAC_Xt
+ bitset<NUM_MISCREG_INFOS>(string("10101010100000000101")),
+ // MISCREG_DC_ISW_Xt
+ bitset<NUM_MISCREG_INFOS>(string("10101010100000000101")),
+ // MISCREG_AT_S1E1R_Xt
+ bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")),
+ // MISCREG_AT_S1E1W_Xt
+ bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")),
+ // MISCREG_AT_S1E0R_Xt
+ bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")),
+ // MISCREG_AT_S1E0W_Xt
+ bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")),
+ // MISCREG_DC_CSW_Xt
+ bitset<NUM_MISCREG_INFOS>(string("10101010100000000101")),
+ // MISCREG_DC_CISW_Xt
+ bitset<NUM_MISCREG_INFOS>(string("10101010100000000101")),
+ // MISCREG_DC_ZVA_Xt
+ bitset<NUM_MISCREG_INFOS>(string("10101010100010000101")),
+ // MISCREG_IC_IVAU_Xt
+ bitset<NUM_MISCREG_INFOS>(string("10101010101010000001")),
+ // MISCREG_DC_CVAC_Xt
+ bitset<NUM_MISCREG_INFOS>(string("10101010101010000101")),
+ // MISCREG_DC_CVAU_Xt
+ bitset<NUM_MISCREG_INFOS>(string("10101010101010000101")),
+ // MISCREG_DC_CIVAC_Xt
+ bitset<NUM_MISCREG_INFOS>(string("10101010101010000101")),
+ // MISCREG_AT_S1E2R_Xt
+ bitset<NUM_MISCREG_INFOS>(string("10001000000000000001")),
+ // MISCREG_AT_S1E2W_Xt
+ bitset<NUM_MISCREG_INFOS>(string("10001000000000000001")),
+ // MISCREG_AT_S12E1R_Xt
+ bitset<NUM_MISCREG_INFOS>(string("10101000000000000001")),
+ // MISCREG_AT_S12E1W_Xt
+ bitset<NUM_MISCREG_INFOS>(string("10101000000000000001")),
+ // MISCREG_AT_S12E0R_Xt
+ bitset<NUM_MISCREG_INFOS>(string("10101000000000000001")),
+ // MISCREG_AT_S12E0W_Xt
+ bitset<NUM_MISCREG_INFOS>(string("10101000000000000001")),
+ // MISCREG_AT_S1E3R_Xt
+ bitset<NUM_MISCREG_INFOS>(string("10100000000000000001")),
+ // MISCREG_AT_S1E3W_Xt
+ bitset<NUM_MISCREG_INFOS>(string("10100000000000000001")),
+ // MISCREG_TLBI_VMALLE1IS
+ bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")),
+ // MISCREG_TLBI_VAE1IS_Xt
+ bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")),
+ // MISCREG_TLBI_ASIDE1IS_Xt
+ bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")),
+ // MISCREG_TLBI_VAAE1IS_Xt
+ bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")),
+ // MISCREG_TLBI_VALE1IS_Xt
+ bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")),
+ // MISCREG_TLBI_VAALE1IS_Xt
+ bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")),
+ // MISCREG_TLBI_VMALLE1
+ bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")),
+ // MISCREG_TLBI_VAE1_Xt
+ bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")),
+ // MISCREG_TLBI_ASIDE1_Xt
+ bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")),
+ // MISCREG_TLBI_VAAE1_Xt
+ bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")),
+ // MISCREG_TLBI_VALE1_Xt
+ bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")),
+ // MISCREG_TLBI_VAALE1_Xt
+ bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")),
+ // MISCREG_TLBI_IPAS2E1IS_Xt
+ bitset<NUM_MISCREG_INFOS>(string("10101000000000000001")),
+ // MISCREG_TLBI_IPAS2LE1IS_Xt
+ bitset<NUM_MISCREG_INFOS>(string("10101000000000000001")),
+ // MISCREG_TLBI_ALLE2IS
+ bitset<NUM_MISCREG_INFOS>(string("10001000000000000001")),
+ // MISCREG_TLBI_VAE2IS_Xt
+ bitset<NUM_MISCREG_INFOS>(string("10001000000000000001")),
+ // MISCREG_TLBI_ALLE1IS
+ bitset<NUM_MISCREG_INFOS>(string("10101000000000000001")),
+ // MISCREG_TLBI_VALE2IS_Xt
+ bitset<NUM_MISCREG_INFOS>(string("10001000000000000001")),
+ // MISCREG_TLBI_VMALLS12E1IS
+ bitset<NUM_MISCREG_INFOS>(string("10101000000000000001")),
+ // MISCREG_TLBI_IPAS2E1_Xt
+ bitset<NUM_MISCREG_INFOS>(string("10101000000000000001")),
+ // MISCREG_TLBI_IPAS2LE1_Xt
+ bitset<NUM_MISCREG_INFOS>(string("10101000000000000001")),
+ // MISCREG_TLBI_ALLE2
+ bitset<NUM_MISCREG_INFOS>(string("10001000000000000001")),
+ // MISCREG_TLBI_VAE2_Xt
+ bitset<NUM_MISCREG_INFOS>(string("10001000000000000001")),
+ // MISCREG_TLBI_ALLE1
+ bitset<NUM_MISCREG_INFOS>(string("10101000000000000001")),
+ // MISCREG_TLBI_VALE2_Xt
+ bitset<NUM_MISCREG_INFOS>(string("10001000000000000001")),
+ // MISCREG_TLBI_VMALLS12E1
+ bitset<NUM_MISCREG_INFOS>(string("10101000000000000001")),
+ // MISCREG_TLBI_ALLE3IS
+ bitset<NUM_MISCREG_INFOS>(string("10100000000000000001")),
+ // MISCREG_TLBI_VAE3IS_Xt
+ bitset<NUM_MISCREG_INFOS>(string("10100000000000000001")),
+ // MISCREG_TLBI_VALE3IS_Xt
+ bitset<NUM_MISCREG_INFOS>(string("10100000000000000001")),
+ // MISCREG_TLBI_ALLE3
+ bitset<NUM_MISCREG_INFOS>(string("10100000000000000001")),
+ // MISCREG_TLBI_VAE3_Xt
+ bitset<NUM_MISCREG_INFOS>(string("10100000000000000001")),
+ // MISCREG_TLBI_VALE3_Xt
+ bitset<NUM_MISCREG_INFOS>(string("10100000000000000001")),
+ // MISCREG_PMINTENSET_EL1
+ bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
+ // MISCREG_PMINTENCLR_EL1
+ bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
+ // MISCREG_PMCR_EL0
+ bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
+ // MISCREG_PMCNTENSET_EL0
+ bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
+ // MISCREG_PMCNTENCLR_EL0
+ bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
+ // MISCREG_PMOVSCLR_EL0
+ bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
+ // MISCREG_PMSWINC_EL0
+ bitset<NUM_MISCREG_INFOS>(string("10101010101111000001")),
+ // MISCREG_PMSELR_EL0
+ bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
+ // MISCREG_PMCEID0_EL0
+ bitset<NUM_MISCREG_INFOS>(string("01010101011111000001")),
+ // MISCREG_PMCEID1_EL0
+ bitset<NUM_MISCREG_INFOS>(string("01010101011111000001")),
+ // MISCREG_PMCCNTR_EL0
+ bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
+ // MISCREG_PMXEVTYPER_EL0
+ bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
+ // MISCREG_PMCCFILTR_EL0
+ bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
+ // MISCREG_PMXEVCNTR_EL0
+ bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
+ // MISCREG_PMUSERENR_EL0
+ bitset<NUM_MISCREG_INFOS>(string("11111111110101000001")),
+ // MISCREG_PMOVSSET_EL0
+ bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
+ // MISCREG_MAIR_EL1
+ bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
+ // MISCREG_AMAIR_EL1
+ bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
+ // MISCREG_MAIR_EL2
+ bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")),
+ // MISCREG_AMAIR_EL2
+ bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")),
+ // MISCREG_MAIR_EL3
+ bitset<NUM_MISCREG_INFOS>(string("11110000000000000001")),
+ // MISCREG_AMAIR_EL3
+ bitset<NUM_MISCREG_INFOS>(string("11110000000000000001")),
+ // MISCREG_L2CTLR_EL1
+ bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
+ // MISCREG_L2ECTLR_EL1
+ bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
+ // MISCREG_VBAR_EL1
+ bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
+ // MISCREG_RVBAR_EL1
+ bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
+ // MISCREG_ISR_EL1
+ bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
+ // MISCREG_VBAR_EL2
+ bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")),
+ // MISCREG_RVBAR_EL2
+ bitset<NUM_MISCREG_INFOS>(string("01010100000000000001")),
+ // MISCREG_VBAR_EL3
+ bitset<NUM_MISCREG_INFOS>(string("11110000000000000001")),
+ // MISCREG_RVBAR_EL3
+ bitset<NUM_MISCREG_INFOS>(string("01010000000000000001")),
+ // MISCREG_RMR_EL3
+ bitset<NUM_MISCREG_INFOS>(string("11110000000000000001")),
+ // MISCREG_CONTEXTIDR_EL1
+ bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
+ // MISCREG_TPIDR_EL1
+ bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
+ // MISCREG_TPIDR_EL0
+ bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
+ // MISCREG_TPIDRRO_EL0
+ bitset<NUM_MISCREG_INFOS>(string("11111111110101000001")),
+ // MISCREG_TPIDR_EL2
+ bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")),
+ // MISCREG_TPIDR_EL3
+ bitset<NUM_MISCREG_INFOS>(string("11110000000000000001")),
+ // MISCREG_CNTKCTL_EL1
+ bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
+ // MISCREG_CNTFRQ_EL0
+ bitset<NUM_MISCREG_INFOS>(string("11110101010101000001")),
+ // MISCREG_CNTPCT_EL0
+ bitset<NUM_MISCREG_INFOS>(string("01010101010101000001")),
+ // MISCREG_CNTVCT_EL0
+ bitset<NUM_MISCREG_INFOS>(string("01010101010101000011")),
+ // MISCREG_CNTP_TVAL_EL0
+ bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
+ // MISCREG_CNTP_CTL_EL0
+ bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
+ // MISCREG_CNTP_CVAL_EL0
+ bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
+ // MISCREG_CNTV_TVAL_EL0
+ bitset<NUM_MISCREG_INFOS>(string("01111000000000000000")),
+ // MISCREG_CNTV_CTL_EL0
+ bitset<NUM_MISCREG_INFOS>(string("01111000000000000000")),
+ // MISCREG_CNTV_CVAL_EL0
+ bitset<NUM_MISCREG_INFOS>(string("01111000000000000000")),
+ // MISCREG_PMEVCNTR0_EL0
+ bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
+ // MISCREG_PMEVCNTR1_EL0
+ bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
+ // MISCREG_PMEVCNTR2_EL0
+ bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
+ // MISCREG_PMEVCNTR3_EL0
+ bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
+ // MISCREG_PMEVCNTR4_EL0
+ bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
+ // MISCREG_PMEVCNTR5_EL0
+ bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
+ // MISCREG_PMEVTYPER0_EL0
+ bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
+ // MISCREG_PMEVTYPER1_EL0
+ bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
+ // MISCREG_PMEVTYPER2_EL0
+ bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
+ // MISCREG_PMEVTYPER3_EL0
+ bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
+ // MISCREG_PMEVTYPER4_EL0
+ bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
+ // MISCREG_PMEVTYPER5_EL0
+ bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
+ // MISCREG_CNTVOFF_EL2
+ bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")),
+ // MISCREG_CNTHCTL_EL2
+ bitset<NUM_MISCREG_INFOS>(string("01111000000000000000")),
+ // MISCREG_CNTHP_TVAL_EL2
+ bitset<NUM_MISCREG_INFOS>(string("01111000000000000000")),
+ // MISCREG_CNTHP_CTL_EL2
+ bitset<NUM_MISCREG_INFOS>(string("01111000000000000000")),
+ // MISCREG_CNTHP_CVAL_EL2
+ bitset<NUM_MISCREG_INFOS>(string("01111000000000000000")),
+ // MISCREG_CNTPS_TVAL_EL1
+ bitset<NUM_MISCREG_INFOS>(string("01111000000000000000")),
+ // MISCREG_CNTPS_CTL_EL1
+ bitset<NUM_MISCREG_INFOS>(string("01111000000000000000")),
+ // MISCREG_CNTPS_CVAL_EL1
+ bitset<NUM_MISCREG_INFOS>(string("01111000000000000000")),
+ // MISCREG_IL1DATA0_EL1
+ bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
+ // MISCREG_IL1DATA1_EL1
+ bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
+ // MISCREG_IL1DATA2_EL1
+ bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
+ // MISCREG_IL1DATA3_EL1
+ bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
+ // MISCREG_DL1DATA0_EL1
+ bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
+ // MISCREG_DL1DATA1_EL1
+ bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
+ // MISCREG_DL1DATA2_EL1
+ bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
+ // MISCREG_DL1DATA3_EL1
+ bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
+ // MISCREG_DL1DATA4_EL1
+ bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
+ // MISCREG_L2ACTLR_EL1
+ bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
+ // MISCREG_CPUACTLR_EL1
+ bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
+ // MISCREG_CPUECTLR_EL1
+ bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
+ // MISCREG_CPUMERRSR_EL1
+ bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
+ // MISCREG_L2MERRSR_EL1
+ bitset<NUM_MISCREG_INFOS>(string("11111111110000000100")),
+ // MISCREG_CBAR_EL1
+ bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
+
+ // Dummy registers
+ // MISCREG_NOP
+ bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
+ // MISCREG_RAZ
+ bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
+ // MISCREG_CP14_UNIMPL
+ bitset<NUM_MISCREG_INFOS>(string("00000000000000000100")),
+ // MISCREG_CP15_UNIMPL
+ bitset<NUM_MISCREG_INFOS>(string("00000000000000000100")),
+ // MISCREG_A64_UNIMPL
+ bitset<NUM_MISCREG_INFOS>(string("00000000000000000100")),
+ // MISCREG_UNKNOWN
+ bitset<NUM_MISCREG_INFOS>(string("00000000000000000001"))
+};
+
MiscRegIndex
decodeCP15Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
{
return MISCREG_TLBTR;
case 5:
return MISCREG_MPIDR;
+ case 6:
+ return MISCREG_REVIDR;
default:
return MISCREG_MIDR;
}
return MISCREG_CSSELR;
}
break;
+ case 4:
+ if (crm == 0) {
+ if (opc2 == 0)
+ return MISCREG_VPIDR;
+ else if (opc2 == 5)
+ return MISCREG_VMPIDR;
+ }
+ break;
}
break;
case 1:
return MISCREG_NSACR;
}
}
+ } else if (opc1 == 4) {
+ if (crm == 0) {
+ if (opc2 == 0)
+ return MISCREG_HSCTLR;
+ else if (opc2 == 1)
+ return MISCREG_HACTLR;
+ } else if (crm == 1) {
+ switch (opc2) {
+ case 0:
+ return MISCREG_HCR;
+ case 1:
+ return MISCREG_HDCR;
+ case 2:
+ return MISCREG_HCPTR;
+ case 3:
+ return MISCREG_HSTR;
+ case 7:
+ return MISCREG_HACR;
+ }
+ }
}
break;
case 2:
case 2:
return MISCREG_TTBCR;
}
+ } else if (opc1 == 4) {
+ if (crm == 0 && opc2 == 2)
+ return MISCREG_HTCR;
+ else if (crm == 1 && opc2 == 2)
+ return MISCREG_VTCR;
}
break;
case 3:
return MISCREG_AIFSR;
}
}
+ } else if (opc1 == 4) {
+ if (crm == 1) {
+ if (opc2 == 0)
+ return MISCREG_HADFSR;
+ else if (opc2 == 1)
+ return MISCREG_HAIFSR;
+ } else if (crm == 2 && opc2 == 0) {
+ return MISCREG_HSR;
+ }
}
break;
case 6:
case 2:
return MISCREG_IFAR;
}
+ } else if (opc1 == 4 && crm == 0) {
+ switch (opc2) {
+ case 0:
+ return MISCREG_HDFAR;
+ case 2:
+ return MISCREG_HIFAR;
+ case 4:
+ return MISCREG_HPFAR;
+ }
}
break;
case 7:
case 8:
switch (opc2) {
case 0:
- return MISCREG_V2PCWPR;
+ return MISCREG_ATS1CPR;
case 1:
- return MISCREG_V2PCWPW;
+ return MISCREG_ATS1CPW;
case 2:
- return MISCREG_V2PCWUR;
+ return MISCREG_ATS1CUR;
case 3:
- return MISCREG_V2PCWUW;
+ return MISCREG_ATS1CUW;
case 4:
- return MISCREG_V2POWPR;
+ return MISCREG_ATS12NSOPR;
case 5:
- return MISCREG_V2POWPW;
+ return MISCREG_ATS12NSOPW;
case 6:
- return MISCREG_V2POWUR;
+ return MISCREG_ATS12NSOUR;
case 7:
- return MISCREG_V2POWUW;
+ return MISCREG_ATS12NSOUW;
}
break;
case 10:
case 1:
return MISCREG_DCCMVAC;
case 2:
- return MISCREG_MCCSW;
+ return MISCREG_DCCSW;
case 4:
return MISCREG_CP15DSB;
case 5:
}
break;
}
+ } else if (opc1 == 4 && crm == 8) {
+ if (opc2 == 0)
+ return MISCREG_ATS1HR;
+ else if (opc2 == 1)
+ return MISCREG_ATS1HW;
}
break;
case 8:
}
break;
}
+ } else if (opc1 == 4) {
+ if (crm == 3) {
+ switch (opc2) {
+ case 0:
+ return MISCREG_TLBIALLHIS;
+ case 1:
+ return MISCREG_TLBIMVAHIS;
+ case 4:
+ return MISCREG_TLBIALLNSNHIS;
+ }
+ } else if (crm == 7) {
+ switch (opc2) {
+ case 0:
+ return MISCREG_TLBIALLH;
+ case 1:
+ return MISCREG_TLBIMVAH;
+ case 4:
+ return MISCREG_TLBIALLNSNH;
+ }
+ }
}
break;
case 9:
case 0:
return MISCREG_PMCCNTR;
case 1:
- return MISCREG_PMC_OTHER;
+ // Selector is PMSELR.SEL
+ return MISCREG_PMXEVTYPER_PMCCFILTR;
case 2:
return MISCREG_PMXEVCNTR;
}
return MISCREG_PMINTENSET;
case 2:
return MISCREG_PMINTENCLR;
+ case 3:
+ return MISCREG_PMOVSSET;
}
break;
}
switch (opc2) {
case 2: // L2CTLR, L2 Control Register
return MISCREG_L2CTLR;
- default:
- warn("Uknown miscregs: crn:%d crm:%d opc1:%d opc2:%d\n",
- crn,crm, opc1,opc2);
- break;
+ case 3:
+ return MISCREG_L2ECTLR;
}
break;
- default:
- return MISCREG_L2LATENCY;
+ break;
}
}
- //Reserved for Branch Predictor, Cache and TCM operations
break;
case 10:
if (opc1 == 0) {
// crm 0, 1, 4, and 8, with op2 0 - 7, reserved for TLB lockdown
if (crm == 2) { // TEX Remap Registers
if (opc2 == 0) {
- return MISCREG_PRRR;
+ // Selector is TTBCR.EAE
+ return MISCREG_PRRR_MAIR0;
+ } else if (opc2 == 1) {
+ // Selector is TTBCR.EAE
+ return MISCREG_NMRR_MAIR1;
+ }
+ } else if (crm == 3) {
+ if (opc2 == 0) {
+ return MISCREG_AMAIR0;
} else if (opc2 == 1) {
- return MISCREG_NMRR;
+ return MISCREG_AMAIR1;
}
}
+ } else if (opc1 == 4) {
+ // crm 0, 1, 4, and 8, with op2 0 - 7, reserved for TLB lockdown
+ if (crm == 2) {
+ if (opc2 == 0)
+ return MISCREG_HMAIR0;
+ else if (opc2 == 1)
+ return MISCREG_HMAIR1;
+ } else if (crm == 3) {
+ if (opc2 == 0)
+ return MISCREG_HAMAIR0;
+ else if (opc2 == 1)
+ return MISCREG_HAMAIR1;
+ }
}
break;
case 11:
return MISCREG_ISR;
}
}
+ } else if (opc1 == 4) {
+ if (crm == 0 && opc2 == 0)
+ return MISCREG_HVBAR;
}
break;
case 13:
if (crm == 0) {
switch (opc2) {
case 0:
- return MISCREG_FCEIDR;
+ return MISCREG_FCSEIDR;
case 1:
return MISCREG_CONTEXTIDR;
case 2:
return MISCREG_TPIDRPRW;
}
}
+ } else if (opc1 == 4) {
+ if (crm == 0 && opc2 == 2)
+ return MISCREG_HTPIDR;
+ }
+ break;
+ case 14:
+ if (opc1 == 0) {
+ switch (crm) {
+ case 0:
+ if (opc2 == 0)
+ return MISCREG_CNTFRQ;
+ break;
+ case 1:
+ if (opc2 == 0)
+ return MISCREG_CNTKCTL;
+ break;
+ case 2:
+ if (opc2 == 0)
+ return MISCREG_CNTP_TVAL;
+ else if (opc2 == 1)
+ return MISCREG_CNTP_CTL;
+ break;
+ case 3:
+ if (opc2 == 0)
+ return MISCREG_CNTV_TVAL;
+ else if (opc2 == 1)
+ return MISCREG_CNTV_CTL;
+ break;
+ }
+ } else if (opc1 == 4) {
+ if (crm == 1 && opc2 == 0) {
+ return MISCREG_CNTHCTL;
+ } else if (crm == 2) {
+ if (opc2 == 0)
+ return MISCREG_CNTHP_TVAL;
+ else if (opc2 == 1)
+ return MISCREG_CNTHP_CTL;
+ }
}
break;
case 15:
// Implementation defined
- return MISCREG_CRN15;
+ return MISCREG_CP15_UNIMPL;
+ }
+ // Unrecognized register
+ return MISCREG_CP15_UNIMPL;
+}
+
+MiscRegIndex
+decodeCP15Reg64(unsigned crm, unsigned opc1)
+{
+ switch (crm) {
+ case 2:
+ switch (opc1) {
+ case 0:
+ return MISCREG_TTBR0;
+ case 1:
+ return MISCREG_TTBR1;
+ case 4:
+ return MISCREG_HTTBR;
+ case 6:
+ return MISCREG_VTTBR;
+ }
+ break;
+ case 7:
+ if (opc1 == 0)
+ return MISCREG_PAR;
+ break;
+ case 14:
+ switch (opc1) {
+ case 0:
+ return MISCREG_CNTPCT;
+ case 1:
+ return MISCREG_CNTVCT;
+ case 2:
+ return MISCREG_CNTP_CVAL;
+ case 3:
+ return MISCREG_CNTV_CVAL;
+ case 4:
+ return MISCREG_CNTVOFF;
+ case 6:
+ return MISCREG_CNTHP_CVAL;
+ }
+ break;
+ case 15:
+ if (opc1 == 0)
+ return MISCREG_CPUMERRSR;
+ else if (opc1 == 1)
+ return MISCREG_L2MERRSR;
+ break;
}
// Unrecognized register
- return NUM_MISCREGS;
+ return MISCREG_CP15_UNIMPL;
+}
+
+bool
+canReadCoprocReg(MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc)
+{
+ bool secure = !scr.ns;
+ bool canRead;
+
+ switch (cpsr.mode) {
+ case MODE_USER:
+ canRead = secure ? miscRegInfo[reg][MISCREG_USR_S_RD] :
+ miscRegInfo[reg][MISCREG_USR_NS_RD];
+ break;
+ case MODE_FIQ:
+ case MODE_IRQ:
+ case MODE_SVC:
+ case MODE_ABORT:
+ case MODE_UNDEFINED:
+ case MODE_SYSTEM:
+ canRead = secure ? miscRegInfo[reg][MISCREG_PRI_S_RD] :
+ miscRegInfo[reg][MISCREG_PRI_NS_RD];
+ break;
+ case MODE_MON:
+ canRead = secure ? miscRegInfo[reg][MISCREG_MON_NS0_RD] :
+ miscRegInfo[reg][MISCREG_MON_NS1_RD];
+ break;
+ case MODE_HYP:
+ canRead = miscRegInfo[reg][MISCREG_HYP_RD];
+ break;
+ default:
+ panic("Unrecognized mode setting in CPSR.\n");
+ }
+ // can't do permissions checkes on the root of a banked pair of regs
+ assert(!miscRegInfo[reg][MISCREG_BANKED]);
+ return canRead;
+}
+
+bool
+canWriteCoprocReg(MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc)
+{
+ bool secure = !scr.ns;
+ bool canWrite;
+
+ switch (cpsr.mode) {
+ case MODE_USER:
+ canWrite = secure ? miscRegInfo[reg][MISCREG_USR_S_WR] :
+ miscRegInfo[reg][MISCREG_USR_NS_WR];
+ break;
+ case MODE_FIQ:
+ case MODE_IRQ:
+ case MODE_SVC:
+ case MODE_ABORT:
+ case MODE_UNDEFINED:
+ case MODE_SYSTEM:
+ canWrite = secure ? miscRegInfo[reg][MISCREG_PRI_S_WR] :
+ miscRegInfo[reg][MISCREG_PRI_NS_WR];
+ break;
+ case MODE_MON:
+ canWrite = secure ? miscRegInfo[reg][MISCREG_MON_NS0_WR] :
+ miscRegInfo[reg][MISCREG_MON_NS1_WR];
+ break;
+ case MODE_HYP:
+ canWrite = miscRegInfo[reg][MISCREG_HYP_WR];
+ break;
+ default:
+ panic("Unrecognized mode setting in CPSR.\n");
+ }
+ // can't do permissions checkes on the root of a banked pair of regs
+ assert(!miscRegInfo[reg][MISCREG_BANKED]);
+ return canWrite;
+}
+
+int
+flattenMiscRegNsBanked(MiscRegIndex reg, ThreadContext *tc)
+{
+ int reg_as_int = static_cast<int>(reg);
+ if (miscRegInfo[reg][MISCREG_BANKED]) {
+ SCR scr = tc->readMiscReg(MISCREG_SCR);
+ reg_as_int += (ArmSystem::haveSecurity(tc) && !scr.ns) ? 2 : 1;
+ }
+ return reg_as_int;
}
+int
+flattenMiscRegNsBanked(MiscRegIndex reg, ThreadContext *tc, bool ns)
+{
+ int reg_as_int = static_cast<int>(reg);
+ if (miscRegInfo[reg][MISCREG_BANKED]) {
+ reg_as_int += (ArmSystem::haveSecurity(tc) && !ns) ? 2 : 1;
+ }
+ return reg_as_int;
+}
+
+
+/**
+ * If the reg is a child reg of a banked set, then the parent is the last
+ * banked one in the list. This is messy, and the wish is to eventually have
+ * the bitmap replaced with a better data structure. the preUnflatten function
+ * initializes a lookup table to speed up the search for these banked
+ * registers.
+ */
+
+int unflattenResultMiscReg[NUM_MISCREGS];
+
+void
+preUnflattenMiscReg()
+{
+ int reg = -1;
+ for (int i = 0 ; i < NUM_MISCREGS; i++){
+ if (miscRegInfo[i][MISCREG_BANKED])
+ reg = i;
+ if (miscRegInfo[i][MISCREG_BANKED_CHILD])
+ unflattenResultMiscReg[i] = reg;
+ else
+ unflattenResultMiscReg[i] = i;
+ // if this assert fails, no parent was found, and something is broken
+ assert(unflattenResultMiscReg[i] > -1);
+ }
+}
+
+int
+unflattenMiscReg(int reg)
+{
+ return unflattenResultMiscReg[reg];
+}
+
+bool
+canReadAArch64SysReg(MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc)
+{
+ // Check for SP_EL0 access while SPSEL == 0
+ if ((reg == MISCREG_SP_EL0) && (tc->readMiscReg(MISCREG_SPSEL) == 0))
+ return false;
+
+ // Check for RVBAR access
+ if (reg == MISCREG_RVBAR_EL1) {
+ ExceptionLevel highest_el = ArmSystem::highestEL(tc);
+ if (highest_el == EL2 || highest_el == EL3)
+ return false;
+ }
+ if (reg == MISCREG_RVBAR_EL2) {
+ ExceptionLevel highest_el = ArmSystem::highestEL(tc);
+ if (highest_el == EL3)
+ return false;
+ }
+
+ bool secure = ArmSystem::haveSecurity(tc) && !scr.ns;
+
+ switch (opModeToEL((OperatingMode) (uint8_t) cpsr.mode)) {
+ case EL0:
+ return secure ? miscRegInfo[reg][MISCREG_USR_S_RD] :
+ miscRegInfo[reg][MISCREG_USR_NS_RD];
+ case EL1:
+ return secure ? miscRegInfo[reg][MISCREG_PRI_S_RD] :
+ miscRegInfo[reg][MISCREG_PRI_NS_RD];
+ // @todo: uncomment this to enable Virtualization
+ // case EL2:
+ // return miscRegInfo[reg][MISCREG_HYP_RD];
+ case EL3:
+ return secure ? miscRegInfo[reg][MISCREG_MON_NS0_RD] :
+ miscRegInfo[reg][MISCREG_MON_NS1_RD];
+ default:
+ panic("Invalid exception level");
+ }
+}
+
+bool
+canWriteAArch64SysReg(MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc)
+{
+ // Check for SP_EL0 access while SPSEL == 0
+ if ((reg == MISCREG_SP_EL0) && (tc->readMiscReg(MISCREG_SPSEL) == 0))
+ return false;
+ ExceptionLevel el = opModeToEL((OperatingMode) (uint8_t) cpsr.mode);
+ if (reg == MISCREG_DAIF) {
+ SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1);
+ if (el == EL0 && !sctlr.uma)
+ return false;
+ }
+ if (reg == MISCREG_DC_ZVA_Xt) {
+ SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1);
+ if (el == EL0 && !sctlr.dze)
+ return false;
+ }
+ if (reg == MISCREG_DC_CVAC_Xt || reg == MISCREG_DC_CIVAC_Xt) {
+ SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1);
+ if (el == EL0 && !sctlr.uci)
+ return false;
+ }
+
+ bool secure = ArmSystem::haveSecurity(tc) && !scr.ns;
+
+ switch (el) {
+ case EL0:
+ return secure ? miscRegInfo[reg][MISCREG_USR_S_WR] :
+ miscRegInfo[reg][MISCREG_USR_NS_WR];
+ case EL1:
+ return secure ? miscRegInfo[reg][MISCREG_PRI_S_WR] :
+ miscRegInfo[reg][MISCREG_PRI_NS_WR];
+ // @todo: uncomment this to enable Virtualization
+ // case EL2:
+ // return miscRegInfo[reg][MISCREG_HYP_WR];
+ case EL3:
+ return secure ? miscRegInfo[reg][MISCREG_MON_NS0_WR] :
+ miscRegInfo[reg][MISCREG_MON_NS1_WR];
+ default:
+ panic("Invalid exception level");
+ }
}
+
+MiscRegIndex
+decodeAArch64SysReg(unsigned op0, unsigned op1,
+ unsigned crn, unsigned crm,
+ unsigned op2)
+{
+ switch (op0) {
+ case 1:
+ switch (crn) {
+ case 7:
+ switch (op1) {
+ case 0:
+ switch (crm) {
+ case 1:
+ switch (op2) {
+ case 0:
+ return MISCREG_IC_IALLUIS;
+ }
+ break;
+ case 5:
+ switch (op2) {
+ case 0:
+ return MISCREG_IC_IALLU;
+ }
+ break;
+ case 6:
+ switch (op2) {
+ case 1:
+ return MISCREG_DC_IVAC_Xt;
+ case 2:
+ return MISCREG_DC_ISW_Xt;
+ }
+ break;
+ case 8:
+ switch (op2) {
+ case 0:
+ return MISCREG_AT_S1E1R_Xt;
+ case 1:
+ return MISCREG_AT_S1E1W_Xt;
+ case 2:
+ return MISCREG_AT_S1E0R_Xt;
+ case 3:
+ return MISCREG_AT_S1E0W_Xt;
+ }
+ break;
+ case 10:
+ switch (op2) {
+ case 2:
+ return MISCREG_DC_CSW_Xt;
+ }
+ break;
+ case 14:
+ switch (op2) {
+ case 2:
+ return MISCREG_DC_CISW_Xt;
+ }
+ break;
+ }
+ break;
+ case 3:
+ switch (crm) {
+ case 4:
+ switch (op2) {
+ case 1:
+ return MISCREG_DC_ZVA_Xt;
+ }
+ break;
+ case 5:
+ switch (op2) {
+ case 1:
+ return MISCREG_IC_IVAU_Xt;
+ }
+ break;
+ case 10:
+ switch (op2) {
+ case 1:
+ return MISCREG_DC_CVAC_Xt;
+ }
+ break;
+ case 11:
+ switch (op2) {
+ case 1:
+ return MISCREG_DC_CVAU_Xt;
+ }
+ break;
+ case 14:
+ switch (op2) {
+ case 1:
+ return MISCREG_DC_CIVAC_Xt;
+ }
+ break;
+ }
+ break;
+ case 4:
+ switch (crm) {
+ case 8:
+ switch (op2) {
+ case 0:
+ return MISCREG_AT_S1E2R_Xt;
+ case 1:
+ return MISCREG_AT_S1E2W_Xt;
+ case 4:
+ return MISCREG_AT_S12E1R_Xt;
+ case 5:
+ return MISCREG_AT_S12E1W_Xt;
+ case 6:
+ return MISCREG_AT_S12E0R_Xt;
+ case 7:
+ return MISCREG_AT_S12E0W_Xt;
+ }
+ break;
+ }
+ break;
+ case 6:
+ switch (crm) {
+ case 8:
+ switch (op2) {
+ case 0:
+ return MISCREG_AT_S1E3R_Xt;
+ case 1:
+ return MISCREG_AT_S1E3W_Xt;
+ }
+ break;
+ }
+ break;
+ }
+ break;
+ case 8:
+ switch (op1) {
+ case 0:
+ switch (crm) {
+ case 3:
+ switch (op2) {
+ case 0:
+ return MISCREG_TLBI_VMALLE1IS;
+ case 1:
+ return MISCREG_TLBI_VAE1IS_Xt;
+ case 2:
+ return MISCREG_TLBI_ASIDE1IS_Xt;
+ case 3:
+ return MISCREG_TLBI_VAAE1IS_Xt;
+ case 5:
+ return MISCREG_TLBI_VALE1IS_Xt;
+ case 7:
+ return MISCREG_TLBI_VAALE1IS_Xt;
+ }
+ break;
+ case 7:
+ switch (op2) {
+ case 0:
+ return MISCREG_TLBI_VMALLE1;
+ case 1:
+ return MISCREG_TLBI_VAE1_Xt;
+ case 2:
+ return MISCREG_TLBI_ASIDE1_Xt;
+ case 3:
+ return MISCREG_TLBI_VAAE1_Xt;
+ case 5:
+ return MISCREG_TLBI_VALE1_Xt;
+ case 7:
+ return MISCREG_TLBI_VAALE1_Xt;
+ }
+ break;
+ }
+ break;
+ case 4:
+ switch (crm) {
+ case 0:
+ switch (op2) {
+ case 1:
+ return MISCREG_TLBI_IPAS2E1IS_Xt;
+ case 5:
+ return MISCREG_TLBI_IPAS2LE1IS_Xt;
+ }
+ break;
+ case 3:
+ switch (op2) {
+ case 0:
+ return MISCREG_TLBI_ALLE2IS;
+ case 1:
+ return MISCREG_TLBI_VAE2IS_Xt;
+ case 4:
+ return MISCREG_TLBI_ALLE1IS;
+ case 5:
+ return MISCREG_TLBI_VALE2IS_Xt;
+ case 6:
+ return MISCREG_TLBI_VMALLS12E1IS;
+ }
+ break;
+ case 4:
+ switch (op2) {
+ case 1:
+ return MISCREG_TLBI_IPAS2E1_Xt;
+ case 5:
+ return MISCREG_TLBI_IPAS2LE1_Xt;
+ }
+ break;
+ case 7:
+ switch (op2) {
+ case 0:
+ return MISCREG_TLBI_ALLE2;
+ case 1:
+ return MISCREG_TLBI_VAE2_Xt;
+ case 4:
+ return MISCREG_TLBI_ALLE1;
+ case 5:
+ return MISCREG_TLBI_VALE2_Xt;
+ case 6:
+ return MISCREG_TLBI_VMALLS12E1;
+ }
+ break;
+ }
+ break;
+ case 6:
+ switch (crm) {
+ case 3:
+ switch (op2) {
+ case 0:
+ return MISCREG_TLBI_ALLE3IS;
+ case 1:
+ return MISCREG_TLBI_VAE3IS_Xt;
+ case 5:
+ return MISCREG_TLBI_VALE3IS_Xt;
+ }
+ break;
+ case 7:
+ switch (op2) {
+ case 0:
+ return MISCREG_TLBI_ALLE3;
+ case 1:
+ return MISCREG_TLBI_VAE3_Xt;
+ case 5:
+ return MISCREG_TLBI_VALE3_Xt;
+ }
+ break;
+ }
+ break;
+ }
+ break;
+ }
+ break;
+ case 2:
+ switch (crn) {
+ case 0:
+ switch (op1) {
+ case 0:
+ switch (crm) {
+ case 0:
+ switch (op2) {
+ case 2:
+ return MISCREG_OSDTRRX_EL1;
+ case 4:
+ return MISCREG_DBGBVR0_EL1;
+ case 5:
+ return MISCREG_DBGBCR0_EL1;
+ case 6:
+ return MISCREG_DBGWVR0_EL1;
+ case 7:
+ return MISCREG_DBGWCR0_EL1;
+ }
+ break;
+ case 1:
+ switch (op2) {
+ case 4:
+ return MISCREG_DBGBVR1_EL1;
+ case 5:
+ return MISCREG_DBGBCR1_EL1;
+ case 6:
+ return MISCREG_DBGWVR1_EL1;
+ case 7:
+ return MISCREG_DBGWCR1_EL1;
+ }
+ break;
+ case 2:
+ switch (op2) {
+ case 0:
+ return MISCREG_MDCCINT_EL1;
+ case 2:
+ return MISCREG_MDSCR_EL1;
+ case 4:
+ return MISCREG_DBGBVR2_EL1;
+ case 5:
+ return MISCREG_DBGBCR2_EL1;
+ case 6:
+ return MISCREG_DBGWVR2_EL1;
+ case 7:
+ return MISCREG_DBGWCR2_EL1;
+ }
+ break;
+ case 3:
+ switch (op2) {
+ case 2:
+ return MISCREG_OSDTRTX_EL1;
+ case 4:
+ return MISCREG_DBGBVR3_EL1;
+ case 5:
+ return MISCREG_DBGBCR3_EL1;
+ case 6:
+ return MISCREG_DBGWVR3_EL1;
+ case 7:
+ return MISCREG_DBGWCR3_EL1;
+ }
+ break;
+ case 4:
+ switch (op2) {
+ case 4:
+ return MISCREG_DBGBVR4_EL1;
+ case 5:
+ return MISCREG_DBGBCR4_EL1;
+ }
+ break;
+ case 5:
+ switch (op2) {
+ case 4:
+ return MISCREG_DBGBVR5_EL1;
+ case 5:
+ return MISCREG_DBGBCR5_EL1;
+ }
+ break;
+ case 6:
+ switch (op2) {
+ case 2:
+ return MISCREG_OSECCR_EL1;
+ }
+ break;
+ }
+ break;
+ case 2:
+ switch (crm) {
+ case 0:
+ switch (op2) {
+ case 0:
+ return MISCREG_TEECR32_EL1;
+ }
+ break;
+ }
+ break;
+ case 3:
+ switch (crm) {
+ case 1:
+ switch (op2) {
+ case 0:
+ return MISCREG_MDCCSR_EL0;
+ }
+ break;
+ case 4:
+ switch (op2) {
+ case 0:
+ return MISCREG_MDDTR_EL0;
+ }
+ break;
+ case 5:
+ switch (op2) {
+ case 0:
+ return MISCREG_MDDTRRX_EL0;
+ }
+ break;
+ }
+ break;
+ case 4:
+ switch (crm) {
+ case 7:
+ switch (op2) {
+ case 0:
+ return MISCREG_DBGVCR32_EL2;
+ }
+ break;
+ }
+ break;
+ }
+ break;
+ case 1:
+ switch (op1) {
+ case 0:
+ switch (crm) {
+ case 0:
+ switch (op2) {
+ case 0:
+ return MISCREG_MDRAR_EL1;
+ case 4:
+ return MISCREG_OSLAR_EL1;
+ }
+ break;
+ case 1:
+ switch (op2) {
+ case 4:
+ return MISCREG_OSLSR_EL1;
+ }
+ break;
+ case 3:
+ switch (op2) {
+ case 4:
+ return MISCREG_OSDLR_EL1;
+ }
+ break;
+ case 4:
+ switch (op2) {
+ case 4:
+ return MISCREG_DBGPRCR_EL1;
+ }
+ break;
+ }
+ break;
+ case 2:
+ switch (crm) {
+ case 0:
+ switch (op2) {
+ case 0:
+ return MISCREG_TEEHBR32_EL1;
+ }
+ break;
+ }
+ break;
+ }
+ break;
+ case 7:
+ switch (op1) {
+ case 0:
+ switch (crm) {
+ case 8:
+ switch (op2) {
+ case 6:
+ return MISCREG_DBGCLAIMSET_EL1;
+ }
+ break;
+ case 9:
+ switch (op2) {
+ case 6:
+ return MISCREG_DBGCLAIMCLR_EL1;
+ }
+ break;
+ case 14:
+ switch (op2) {
+ case 6:
+ return MISCREG_DBGAUTHSTATUS_EL1;
+ }
+ break;
+ }
+ break;
+ }
+ break;
+ }
+ break;
+ case 3:
+ switch (crn) {
+ case 0:
+ switch (op1) {
+ case 0:
+ switch (crm) {
+ case 0:
+ switch (op2) {
+ case 0:
+ return MISCREG_MIDR_EL1;
+ case 5:
+ return MISCREG_MPIDR_EL1;
+ case 6:
+ return MISCREG_REVIDR_EL1;
+ }
+ break;
+ case 1:
+ switch (op2) {
+ case 0:
+ return MISCREG_ID_PFR0_EL1;
+ case 1:
+ return MISCREG_ID_PFR1_EL1;
+ case 2:
+ return MISCREG_ID_DFR0_EL1;
+ case 3:
+ return MISCREG_ID_AFR0_EL1;
+ case 4:
+ return MISCREG_ID_MMFR0_EL1;
+ case 5:
+ return MISCREG_ID_MMFR1_EL1;
+ case 6:
+ return MISCREG_ID_MMFR2_EL1;
+ case 7:
+ return MISCREG_ID_MMFR3_EL1;
+ }
+ break;
+ case 2:
+ switch (op2) {
+ case 0:
+ return MISCREG_ID_ISAR0_EL1;
+ case 1:
+ return MISCREG_ID_ISAR1_EL1;
+ case 2:
+ return MISCREG_ID_ISAR2_EL1;
+ case 3:
+ return MISCREG_ID_ISAR3_EL1;
+ case 4:
+ return MISCREG_ID_ISAR4_EL1;
+ case 5:
+ return MISCREG_ID_ISAR5_EL1;
+ }
+ break;
+ case 3:
+ switch (op2) {
+ case 0:
+ return MISCREG_MVFR0_EL1;
+ case 1:
+ return MISCREG_MVFR1_EL1;
+ case 2:
+ return MISCREG_MVFR2_EL1;
+ case 3 ... 7:
+ return MISCREG_RAZ;
+ }
+ break;
+ case 4:
+ switch (op2) {
+ case 0:
+ return MISCREG_ID_AA64PFR0_EL1;
+ case 1:
+ return MISCREG_ID_AA64PFR1_EL1;
+ case 2 ... 7:
+ return MISCREG_RAZ;
+ }
+ break;
+ case 5:
+ switch (op2) {
+ case 0:
+ return MISCREG_ID_AA64DFR0_EL1;
+ case 1:
+ return MISCREG_ID_AA64DFR1_EL1;
+ case 4:
+ return MISCREG_ID_AA64AFR0_EL1;
+ case 5:
+ return MISCREG_ID_AA64AFR1_EL1;
+ case 2:
+ case 3:
+ case 6:
+ case 7:
+ return MISCREG_RAZ;
+ }
+ break;
+ case 6:
+ switch (op2) {
+ case 0:
+ return MISCREG_ID_AA64ISAR0_EL1;
+ case 1:
+ return MISCREG_ID_AA64ISAR1_EL1;
+ case 2 ... 7:
+ return MISCREG_RAZ;
+ }
+ break;
+ case 7:
+ switch (op2) {
+ case 0:
+ return MISCREG_ID_AA64MMFR0_EL1;
+ case 1:
+ return MISCREG_ID_AA64MMFR1_EL1;
+ case 2 ... 7:
+ return MISCREG_RAZ;
+ }
+ break;
+ }
+ break;
+ case 1:
+ switch (crm) {
+ case 0:
+ switch (op2) {
+ case 0:
+ return MISCREG_CCSIDR_EL1;
+ case 1:
+ return MISCREG_CLIDR_EL1;
+ case 7:
+ return MISCREG_AIDR_EL1;
+ }
+ break;
+ }
+ break;
+ case 2:
+ switch (crm) {
+ case 0:
+ switch (op2) {
+ case 0:
+ return MISCREG_CSSELR_EL1;
+ }
+ break;
+ }
+ break;
+ case 3:
+ switch (crm) {
+ case 0:
+ switch (op2) {
+ case 1:
+ return MISCREG_CTR_EL0;
+ case 7:
+ return MISCREG_DCZID_EL0;
+ }
+ break;
+ }
+ break;
+ case 4:
+ switch (crm) {
+ case 0:
+ switch (op2) {
+ case 0:
+ return MISCREG_VPIDR_EL2;
+ case 5:
+ return MISCREG_VMPIDR_EL2;
+ }
+ break;
+ }
+ break;
+ }
+ break;
+ case 1:
+ switch (op1) {
+ case 0:
+ switch (crm) {
+ case 0:
+ switch (op2) {
+ case 0:
+ return MISCREG_SCTLR_EL1;
+ case 1:
+ return MISCREG_ACTLR_EL1;
+ case 2:
+ return MISCREG_CPACR_EL1;
+ }
+ break;
+ }
+ break;
+ case 4:
+ switch (crm) {
+ case 0:
+ switch (op2) {
+ case 0:
+ return MISCREG_SCTLR_EL2;
+ case 1:
+ return MISCREG_ACTLR_EL2;
+ }
+ break;
+ case 1:
+ switch (op2) {
+ case 0:
+ return MISCREG_HCR_EL2;
+ case 1:
+ return MISCREG_MDCR_EL2;
+ case 2:
+ return MISCREG_CPTR_EL2;
+ case 3:
+ return MISCREG_HSTR_EL2;
+ case 7:
+ return MISCREG_HACR_EL2;
+ }
+ break;
+ }
+ break;
+ case 6:
+ switch (crm) {
+ case 0:
+ switch (op2) {
+ case 0:
+ return MISCREG_SCTLR_EL3;
+ case 1:
+ return MISCREG_ACTLR_EL3;
+ }
+ break;
+ case 1:
+ switch (op2) {
+ case 0:
+ return MISCREG_SCR_EL3;
+ case 1:
+ return MISCREG_SDER32_EL3;
+ case 2:
+ return MISCREG_CPTR_EL3;
+ }
+ break;
+ case 3:
+ switch (op2) {
+ case 1:
+ return MISCREG_MDCR_EL3;
+ }
+ break;
+ }
+ break;
+ }
+ break;
+ case 2:
+ switch (op1) {
+ case 0:
+ switch (crm) {
+ case 0:
+ switch (op2) {
+ case 0:
+ return MISCREG_TTBR0_EL1;
+ case 1:
+ return MISCREG_TTBR1_EL1;
+ case 2:
+ return MISCREG_TCR_EL1;
+ }
+ break;
+ }
+ break;
+ case 4:
+ switch (crm) {
+ case 0:
+ switch (op2) {
+ case 0:
+ return MISCREG_TTBR0_EL2;
+ case 2:
+ return MISCREG_TCR_EL2;
+ }
+ break;
+ case 1:
+ switch (op2) {
+ case 0:
+ return MISCREG_VTTBR_EL2;
+ case 2:
+ return MISCREG_VTCR_EL2;
+ }
+ break;
+ }
+ break;
+ case 6:
+ switch (crm) {
+ case 0:
+ switch (op2) {
+ case 0:
+ return MISCREG_TTBR0_EL3;
+ case 2:
+ return MISCREG_TCR_EL3;
+ }
+ break;
+ }
+ break;
+ }
+ break;
+ case 3:
+ switch (op1) {
+ case 4:
+ switch (crm) {
+ case 0:
+ switch (op2) {
+ case 0:
+ return MISCREG_DACR32_EL2;
+ }
+ break;
+ }
+ break;
+ }
+ break;
+ case 4:
+ switch (op1) {
+ case 0:
+ switch (crm) {
+ case 0:
+ switch (op2) {
+ case 0:
+ return MISCREG_SPSR_EL1;
+ case 1:
+ return MISCREG_ELR_EL1;
+ }
+ break;
+ case 1:
+ switch (op2) {
+ case 0:
+ return MISCREG_SP_EL0;
+ }
+ break;
+ case 2:
+ switch (op2) {
+ case 0:
+ return MISCREG_SPSEL;
+ case 2:
+ return MISCREG_CURRENTEL;
+ }
+ break;
+ }
+ break;
+ case 3:
+ switch (crm) {
+ case 2:
+ switch (op2) {
+ case 0:
+ return MISCREG_NZCV;
+ case 1:
+ return MISCREG_DAIF;
+ }
+ break;
+ case 4:
+ switch (op2) {
+ case 0:
+ return MISCREG_FPCR;
+ case 1:
+ return MISCREG_FPSR;
+ }
+ break;
+ case 5:
+ switch (op2) {
+ case 0:
+ return MISCREG_DSPSR_EL0;
+ case 1:
+ return MISCREG_DLR_EL0;
+ }
+ break;
+ }
+ break;
+ case 4:
+ switch (crm) {
+ case 0:
+ switch (op2) {
+ case 0:
+ return MISCREG_SPSR_EL2;
+ case 1:
+ return MISCREG_ELR_EL2;
+ }
+ break;
+ case 1:
+ switch (op2) {
+ case 0:
+ return MISCREG_SP_EL1;
+ }
+ break;
+ case 3:
+ switch (op2) {
+ case 0:
+ return MISCREG_SPSR_IRQ_AA64;
+ case 1:
+ return MISCREG_SPSR_ABT_AA64;
+ case 2:
+ return MISCREG_SPSR_UND_AA64;
+ case 3:
+ return MISCREG_SPSR_FIQ_AA64;
+ }
+ break;
+ }
+ break;
+ case 6:
+ switch (crm) {
+ case 0:
+ switch (op2) {
+ case 0:
+ return MISCREG_SPSR_EL3;
+ case 1:
+ return MISCREG_ELR_EL3;
+ }
+ break;
+ case 1:
+ switch (op2) {
+ case 0:
+ return MISCREG_SP_EL2;
+ }
+ break;
+ }
+ break;
+ }
+ break;
+ case 5:
+ switch (op1) {
+ case 0:
+ switch (crm) {
+ case 1:
+ switch (op2) {
+ case 0:
+ return MISCREG_AFSR0_EL1;
+ case 1:
+ return MISCREG_AFSR1_EL1;
+ }
+ break;
+ case 2:
+ switch (op2) {
+ case 0:
+ return MISCREG_ESR_EL1;
+ }
+ break;
+ }
+ break;
+ case 4:
+ switch (crm) {
+ case 0:
+ switch (op2) {
+ case 1:
+ return MISCREG_IFSR32_EL2;
+ }
+ break;
+ case 1:
+ switch (op2) {
+ case 0:
+ return MISCREG_AFSR0_EL2;
+ case 1:
+ return MISCREG_AFSR1_EL2;
+ }
+ break;
+ case 2:
+ switch (op2) {
+ case 0:
+ return MISCREG_ESR_EL2;
+ }
+ break;
+ case 3:
+ switch (op2) {
+ case 0:
+ return MISCREG_FPEXC32_EL2;
+ }
+ break;
+ }
+ break;
+ case 6:
+ switch (crm) {
+ case 1:
+ switch (op2) {
+ case 0:
+ return MISCREG_AFSR0_EL3;
+ case 1:
+ return MISCREG_AFSR1_EL3;
+ }
+ break;
+ case 2:
+ switch (op2) {
+ case 0:
+ return MISCREG_ESR_EL3;
+ }
+ break;
+ }
+ break;
+ }
+ break;
+ case 6:
+ switch (op1) {
+ case 0:
+ switch (crm) {
+ case 0:
+ switch (op2) {
+ case 0:
+ return MISCREG_FAR_EL1;
+ }
+ break;
+ }
+ break;
+ case 4:
+ switch (crm) {
+ case 0:
+ switch (op2) {
+ case 0:
+ return MISCREG_FAR_EL2;
+ case 4:
+ return MISCREG_HPFAR_EL2;
+ }
+ break;
+ }
+ break;
+ case 6:
+ switch (crm) {
+ case 0:
+ switch (op2) {
+ case 0:
+ return MISCREG_FAR_EL3;
+ }
+ break;
+ }
+ break;
+ }
+ break;
+ case 7:
+ switch (op1) {
+ case 0:
+ switch (crm) {
+ case 4:
+ switch (op2) {
+ case 0:
+ return MISCREG_PAR_EL1;
+ }
+ break;
+ }
+ break;
+ }
+ break;
+ case 9:
+ switch (op1) {
+ case 0:
+ switch (crm) {
+ case 14:
+ switch (op2) {
+ case 1:
+ return MISCREG_PMINTENSET_EL1;
+ case 2:
+ return MISCREG_PMINTENCLR_EL1;
+ }
+ break;
+ }
+ break;
+ case 3:
+ switch (crm) {
+ case 12:
+ switch (op2) {
+ case 0:
+ return MISCREG_PMCR_EL0;
+ case 1:
+ return MISCREG_PMCNTENSET_EL0;
+ case 2:
+ return MISCREG_PMCNTENCLR_EL0;
+ case 3:
+ return MISCREG_PMOVSCLR_EL0;
+ case 4:
+ return MISCREG_PMSWINC_EL0;
+ case 5:
+ return MISCREG_PMSELR_EL0;
+ case 6:
+ return MISCREG_PMCEID0_EL0;
+ case 7:
+ return MISCREG_PMCEID1_EL0;
+ }
+ break;
+ case 13:
+ switch (op2) {
+ case 0:
+ return MISCREG_PMCCNTR_EL0;
+ case 1:
+ return MISCREG_PMXEVTYPER_EL0;
+ case 2:
+ return MISCREG_PMXEVCNTR_EL0;
+ }
+ break;
+ case 14:
+ switch (op2) {
+ case 0:
+ return MISCREG_PMUSERENR_EL0;
+ case 3:
+ return MISCREG_PMOVSSET_EL0;
+ }
+ break;
+ }
+ break;
+ }
+ break;
+ case 10:
+ switch (op1) {
+ case 0:
+ switch (crm) {
+ case 2:
+ switch (op2) {
+ case 0:
+ return MISCREG_MAIR_EL1;
+ }
+ break;
+ case 3:
+ switch (op2) {
+ case 0:
+ return MISCREG_AMAIR_EL1;
+ }
+ break;
+ }
+ break;
+ case 4:
+ switch (crm) {
+ case 2:
+ switch (op2) {
+ case 0:
+ return MISCREG_MAIR_EL2;
+ }
+ break;
+ case 3:
+ switch (op2) {
+ case 0:
+ return MISCREG_AMAIR_EL2;
+ }
+ break;
+ }
+ break;
+ case 6:
+ switch (crm) {
+ case 2:
+ switch (op2) {
+ case 0:
+ return MISCREG_MAIR_EL3;
+ }
+ break;
+ case 3:
+ switch (op2) {
+ case 0:
+ return MISCREG_AMAIR_EL3;
+ }
+ break;
+ }
+ break;
+ }
+ break;
+ case 11:
+ switch (op1) {
+ case 1:
+ switch (crm) {
+ case 0:
+ switch (op2) {
+ case 2:
+ return MISCREG_L2CTLR_EL1;
+ case 3:
+ return MISCREG_L2ECTLR_EL1;
+ }
+ break;
+ }
+ break;
+ }
+ break;
+ case 12:
+ switch (op1) {
+ case 0:
+ switch (crm) {
+ case 0:
+ switch (op2) {
+ case 0:
+ return MISCREG_VBAR_EL1;
+ case 1:
+ return MISCREG_RVBAR_EL1;
+ }
+ break;
+ case 1:
+ switch (op2) {
+ case 0:
+ return MISCREG_ISR_EL1;
+ }
+ break;
+ }
+ break;
+ case 4:
+ switch (crm) {
+ case 0:
+ switch (op2) {
+ case 0:
+ return MISCREG_VBAR_EL2;
+ case 1:
+ return MISCREG_RVBAR_EL2;
+ }
+ break;
+ }
+ break;
+ case 6:
+ switch (crm) {
+ case 0:
+ switch (op2) {
+ case 0:
+ return MISCREG_VBAR_EL3;
+ case 1:
+ return MISCREG_RVBAR_EL3;
+ case 2:
+ return MISCREG_RMR_EL3;
+ }
+ break;
+ }
+ break;
+ }
+ break;
+ case 13:
+ switch (op1) {
+ case 0:
+ switch (crm) {
+ case 0:
+ switch (op2) {
+ case 1:
+ return MISCREG_CONTEXTIDR_EL1;
+ case 4:
+ return MISCREG_TPIDR_EL1;
+ }
+ break;
+ }
+ break;
+ case 3:
+ switch (crm) {
+ case 0:
+ switch (op2) {
+ case 2:
+ return MISCREG_TPIDR_EL0;
+ case 3:
+ return MISCREG_TPIDRRO_EL0;
+ }
+ break;
+ }
+ break;
+ case 4:
+ switch (crm) {
+ case 0:
+ switch (op2) {
+ case 2:
+ return MISCREG_TPIDR_EL2;
+ }
+ break;
+ }
+ break;
+ case 6:
+ switch (crm) {
+ case 0:
+ switch (op2) {
+ case 2:
+ return MISCREG_TPIDR_EL3;
+ }
+ break;
+ }
+ break;
+ }
+ break;
+ case 14:
+ switch (op1) {
+ case 0:
+ switch (crm) {
+ case 1:
+ switch (op2) {
+ case 0:
+ return MISCREG_CNTKCTL_EL1;
+ }
+ break;
+ }
+ break;
+ case 3:
+ switch (crm) {
+ case 0:
+ switch (op2) {
+ case 0:
+ return MISCREG_CNTFRQ_EL0;
+ case 1:
+ return MISCREG_CNTPCT_EL0;
+ case 2:
+ return MISCREG_CNTVCT_EL0;
+ }
+ break;
+ case 2:
+ switch (op2) {
+ case 0:
+ return MISCREG_CNTP_TVAL_EL0;
+ case 1:
+ return MISCREG_CNTP_CTL_EL0;
+ case 2:
+ return MISCREG_CNTP_CVAL_EL0;
+ }
+ break;
+ case 3:
+ switch (op2) {
+ case 0:
+ return MISCREG_CNTV_TVAL_EL0;
+ case 1:
+ return MISCREG_CNTV_CTL_EL0;
+ case 2:
+ return MISCREG_CNTV_CVAL_EL0;
+ }
+ break;
+ case 8:
+ switch (op2) {
+ case 0:
+ return MISCREG_PMEVCNTR0_EL0;
+ case 1:
+ return MISCREG_PMEVCNTR1_EL0;
+ case 2:
+ return MISCREG_PMEVCNTR2_EL0;
+ case 3:
+ return MISCREG_PMEVCNTR3_EL0;
+ case 4:
+ return MISCREG_PMEVCNTR4_EL0;
+ case 5:
+ return MISCREG_PMEVCNTR5_EL0;
+ }
+ break;
+ case 12:
+ switch (op2) {
+ case 0:
+ return MISCREG_PMEVTYPER0_EL0;
+ case 1:
+ return MISCREG_PMEVTYPER1_EL0;
+ case 2:
+ return MISCREG_PMEVTYPER2_EL0;
+ case 3:
+ return MISCREG_PMEVTYPER3_EL0;
+ case 4:
+ return MISCREG_PMEVTYPER4_EL0;
+ case 5:
+ return MISCREG_PMEVTYPER5_EL0;
+ }
+ break;
+ case 15:
+ switch (op2) {
+ case 7:
+ return MISCREG_PMCCFILTR_EL0;
+ }
+ }
+ break;
+ case 4:
+ switch (crm) {
+ case 0:
+ switch (op2) {
+ case 3:
+ return MISCREG_CNTVOFF_EL2;
+ }
+ break;
+ case 1:
+ switch (op2) {
+ case 0:
+ return MISCREG_CNTHCTL_EL2;
+ }
+ break;
+ case 2:
+ switch (op2) {
+ case 0:
+ return MISCREG_CNTHP_TVAL_EL2;
+ case 1:
+ return MISCREG_CNTHP_CTL_EL2;
+ case 2:
+ return MISCREG_CNTHP_CVAL_EL2;
+ }
+ break;
+ }
+ break;
+ case 7:
+ switch (crm) {
+ case 2:
+ switch (op2) {
+ case 0:
+ return MISCREG_CNTPS_TVAL_EL1;
+ case 1:
+ return MISCREG_CNTPS_CTL_EL1;
+ case 2:
+ return MISCREG_CNTPS_CVAL_EL1;
+ }
+ break;
+ }
+ break;
+ }
+ break;
+ case 15:
+ switch (op1) {
+ case 0:
+ switch (crm) {
+ case 0:
+ switch (op2) {
+ case 0:
+ return MISCREG_IL1DATA0_EL1;
+ case 1:
+ return MISCREG_IL1DATA1_EL1;
+ case 2:
+ return MISCREG_IL1DATA2_EL1;
+ case 3:
+ return MISCREG_IL1DATA3_EL1;
+ }
+ break;
+ case 1:
+ switch (op2) {
+ case 0:
+ return MISCREG_DL1DATA0_EL1;
+ case 1:
+ return MISCREG_DL1DATA1_EL1;
+ case 2:
+ return MISCREG_DL1DATA2_EL1;
+ case 3:
+ return MISCREG_DL1DATA3_EL1;
+ case 4:
+ return MISCREG_DL1DATA4_EL1;
+ }
+ break;
+ }
+ break;
+ case 1:
+ switch (crm) {
+ case 0:
+ switch (op2) {
+ case 0:
+ return MISCREG_L2ACTLR_EL1;
+ }
+ break;
+ case 2:
+ switch (op2) {
+ case 0:
+ return MISCREG_CPUACTLR_EL1;
+ case 1:
+ return MISCREG_CPUECTLR_EL1;
+ case 2:
+ return MISCREG_CPUMERRSR_EL1;
+ case 3:
+ return MISCREG_L2MERRSR_EL1;
+ }
+ break;
+ case 3:
+ switch (op2) {
+ case 0:
+ return MISCREG_CBAR_EL1;
+
+ }
+ break;
+ }
+ break;
+ }
+ break;
+ }
+ break;
+ }
+
+ return MISCREG_UNKNOWN;
+}
+
+} // namespace ArmISA
projects / gem5.git / blobdiff