return MISCREG_HDCR;
case 2:
return MISCREG_HCPTR;
+ case 4:
+ return MISCREG_HCR2;
case 3:
return MISCREG_HSTR;
case 7:
return MISCREG_CNTHP_CVAL;
}
break;
+ case 12:
+ switch (opc1) {
+ case 0:
+ return MISCREG_ICC_SGI1R;
+ case 1:
+ return MISCREG_ICC_ASGI1R;
+ case 2:
+ return MISCREG_ICC_SGI0R;
+ default:
+ break;
+ }
+ break;
case 15:
if (opc1 == 0)
return MISCREG_CPUMERRSR;
return reg_as_int;
}
+int
+snsBankedIndex64(MiscRegIndex reg, ThreadContext *tc)
+{
+ SCR scr = tc->readMiscReg(MISCREG_SCR);
+ return tc->getIsaPtr()->snsBankedIndex64(reg, scr.ns);
+}
/**
* If the reg is a child reg of a banked set, then the parent is the last
bool secure = ArmSystem::haveSecurity(tc) && !scr.ns;
- switch (opModeToEL((OperatingMode) (uint8_t) cpsr.mode)) {
+ switch (currEL(cpsr)) {
case EL0:
return secure ? miscRegInfo[reg][MISCREG_USR_S_RD] :
miscRegInfo[reg][MISCREG_USR_NS_RD];
// Check for SP_EL0 access while SPSEL == 0
if ((reg == MISCREG_SP_EL0) && (tc->readMiscReg(MISCREG_SPSEL) == 0))
return false;
- ExceptionLevel el = opModeToEL((OperatingMode) (uint8_t) cpsr.mode);
+ ExceptionLevel el = currEL(cpsr);
if (reg == MISCREG_DAIF) {
SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1);
if (el == EL0 && !sctlr.uma)
InitReg(MISCREG_HACTLR)
.hyp().monNonSecure();
InitReg(MISCREG_HCR)
- .hyp().monNonSecure();
+ .hyp().monNonSecure()
+ .res0(0x90000000);
+ InitReg(MISCREG_HCR2)
+ .hyp().monNonSecure()
+ .res0(0xffa9ff8c);
InitReg(MISCREG_HDCR)
.hyp().monNonSecure();
InitReg(MISCREG_HCPTR)
.mapsTo(MISCREG_HACTLR);
InitReg(MISCREG_HCR_EL2)
.hyp().mon()
- .mapsTo(MISCREG_HCR /*, MISCREG_HCR2*/);
+ .mapsTo(MISCREG_HCR, MISCREG_HCR2);
InitReg(MISCREG_MDCR_EL2)
.hyp().mon()
.mapsTo(MISCREG_HDCR);
.allPrivileges().exceptUserMode()
.mapsTo(MISCREG_ICC_AP0R3);
InitReg(MISCREG_ICC_AP1R0_EL1)
- .banked()
+ .banked64()
.mapsTo(MISCREG_ICC_AP1R0);
InitReg(MISCREG_ICC_AP1R0_EL1_NS)
.bankedChild()
.allPrivileges().exceptUserMode()
.mapsTo(MISCREG_ICC_AP1R0_S);
InitReg(MISCREG_ICC_AP1R1_EL1)
- .banked()
+ .banked64()
.mapsTo(MISCREG_ICC_AP1R1);
InitReg(MISCREG_ICC_AP1R1_EL1_NS)
.bankedChild()
.allPrivileges().exceptUserMode()
.mapsTo(MISCREG_ICC_AP1R1_S);
InitReg(MISCREG_ICC_AP1R2_EL1)
- .banked()
+ .banked64()
.mapsTo(MISCREG_ICC_AP1R2);
InitReg(MISCREG_ICC_AP1R2_EL1_NS)
.bankedChild()
.allPrivileges().exceptUserMode()
.mapsTo(MISCREG_ICC_AP1R2_S);
InitReg(MISCREG_ICC_AP1R3_EL1)
- .banked()
+ .banked64()
.mapsTo(MISCREG_ICC_AP1R3);
InitReg(MISCREG_ICC_AP1R3_EL1_NS)
.bankedChild()
.allPrivileges().exceptUserMode().writes(0)
.mapsTo(MISCREG_ICC_HPPIR1);
InitReg(MISCREG_ICC_BPR1_EL1)
- .banked()
+ .banked64()
.mapsTo(MISCREG_ICC_BPR1);
InitReg(MISCREG_ICC_BPR1_EL1_NS)
.bankedChild()
.secure().exceptUserMode()
.mapsTo(MISCREG_ICC_BPR1_S);
InitReg(MISCREG_ICC_CTLR_EL1)
- .banked()
+ .banked64()
.mapsTo(MISCREG_ICC_CTLR);
InitReg(MISCREG_ICC_CTLR_EL1_NS)
.bankedChild()
.allPrivileges().exceptUserMode()
.mapsTo(MISCREG_ICC_IGRPEN0);
InitReg(MISCREG_ICC_IGRPEN1_EL1)
- .banked()
+ .banked64()
.mapsTo(MISCREG_ICC_IGRPEN1);
InitReg(MISCREG_ICC_IGRPEN1_EL1_NS)
.bankedChild()