/*
- * Copyright (c) 2010-2013, 2015-2019 ARM Limited
+ * Copyright (c) 2010-2013, 2015-2020 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Gabe Black
- * Ali Saidi
- * Giacomo Gabrielli
*/
#include "arch/arm/miscregs.hh"
return MISCREG_HDCR;
case 2:
return MISCREG_HCPTR;
+ case 4:
+ return MISCREG_HCR2;
case 3:
return MISCREG_HSTR;
case 7:
return MISCREG_CNTHP_CVAL;
}
break;
+ case 12:
+ switch (opc1) {
+ case 0:
+ return MISCREG_ICC_SGI1R;
+ case 1:
+ return MISCREG_ICC_ASGI1R;
+ case 2:
+ return MISCREG_ICC_SGI0R;
+ default:
+ break;
+ }
+ break;
case 15:
if (opc1 == 0)
return MISCREG_CPUMERRSR;
return reg_as_int;
}
+int
+snsBankedIndex64(MiscRegIndex reg, ThreadContext *tc)
+{
+ auto *isa = static_cast<ArmISA::ISA *>(tc->getIsaPtr());
+ SCR scr = tc->readMiscReg(MISCREG_SCR);
+ return isa->snsBankedIndex64(reg, scr.ns);
+}
/**
* If the reg is a child reg of a banked set, then the parent is the last
}
bool
-canReadAArch64SysReg(MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc)
+canReadAArch64SysReg(MiscRegIndex reg, HCR hcr, SCR scr, CPSR cpsr,
+ ThreadContext *tc)
{
// Check for SP_EL0 access while SPSEL == 0
if ((reg == MISCREG_SP_EL0) && (tc->readMiscReg(MISCREG_SPSEL) == 0))
}
bool secure = ArmSystem::haveSecurity(tc) && !scr.ns;
+ bool el2_host = EL2Enabled(tc) && hcr.e2h;
- switch (opModeToEL((OperatingMode) (uint8_t) cpsr.mode)) {
+ switch (currEL(cpsr)) {
case EL0:
return secure ? miscRegInfo[reg][MISCREG_USR_S_RD] :
miscRegInfo[reg][MISCREG_USR_NS_RD];
return secure ? miscRegInfo[reg][MISCREG_PRI_S_RD] :
miscRegInfo[reg][MISCREG_PRI_NS_RD];
case EL2:
- return miscRegInfo[reg][MISCREG_HYP_RD];
+ return el2_host ? miscRegInfo[reg][MISCREG_HYP_E2H_RD] :
+ miscRegInfo[reg][MISCREG_HYP_RD];
case EL3:
- return secure ? miscRegInfo[reg][MISCREG_MON_NS0_RD] :
+ return el2_host ? miscRegInfo[reg][MISCREG_MON_E2H_RD] :
+ secure ? miscRegInfo[reg][MISCREG_MON_NS0_RD] :
miscRegInfo[reg][MISCREG_MON_NS1_RD];
default:
panic("Invalid exception level");
}
bool
-canWriteAArch64SysReg(MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc)
+canWriteAArch64SysReg(MiscRegIndex reg, HCR hcr, SCR scr, CPSR cpsr,
+ ThreadContext *tc)
{
// Check for SP_EL0 access while SPSEL == 0
if ((reg == MISCREG_SP_EL0) && (tc->readMiscReg(MISCREG_SPSEL) == 0))
return false;
- ExceptionLevel el = opModeToEL((OperatingMode) (uint8_t) cpsr.mode);
+ ExceptionLevel el = currEL(cpsr);
if (reg == MISCREG_DAIF) {
SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1);
if (el == EL0 && !sctlr.uma)
}
bool secure = ArmSystem::haveSecurity(tc) && !scr.ns;
+ bool el2_host = EL2Enabled(tc) && hcr.e2h;
switch (el) {
case EL0:
return secure ? miscRegInfo[reg][MISCREG_PRI_S_WR] :
miscRegInfo[reg][MISCREG_PRI_NS_WR];
case EL2:
- return miscRegInfo[reg][MISCREG_HYP_WR];
+ return el2_host ? miscRegInfo[reg][MISCREG_HYP_E2H_WR] :
+ miscRegInfo[reg][MISCREG_HYP_WR];
case EL3:
- return secure ? miscRegInfo[reg][MISCREG_MON_NS0_WR] :
+ return el2_host ? miscRegInfo[reg][MISCREG_MON_E2H_WR] :
+ secure ? miscRegInfo[reg][MISCREG_MON_NS0_WR] :
miscRegInfo[reg][MISCREG_MON_NS1_WR];
default:
panic("Invalid exception level");
return MISCREG_TCR_EL1;
}
break;
+ case 0x1:
+ switch (op2) {
+ case 0x0:
+ return MISCREG_APIAKeyLo_EL1;
+ case 0x1:
+ return MISCREG_APIAKeyHi_EL1;
+ case 0x2:
+ return MISCREG_APIBKeyLo_EL1;
+ case 0x3:
+ return MISCREG_APIBKeyHi_EL1;
+ }
+ break;
+ case 0x2:
+ switch (op2) {
+ case 0x0:
+ return MISCREG_APDAKeyLo_EL1;
+ case 0x1:
+ return MISCREG_APDAKeyHi_EL1;
+ case 0x2:
+ return MISCREG_APDBKeyLo_EL1;
+ case 0x3:
+ return MISCREG_APDBKeyHi_EL1;
+ }
+ break;
+
+ case 0x3:
+ switch (op2) {
+ case 0x0:
+ return MISCREG_APGAKeyLo_EL1;
+ case 0x1:
+ return MISCREG_APGAKeyHi_EL1;
+ }
+ break;
}
break;
case 4:
bool nTLSMD = false;
// Pointer authentication (Arm 8.3+), unsupported
- bool EnDA = false; // using APDAKey_EL1 key of instr addrs in ELs 0,1
- bool EnDB = false; // using APDBKey_EL1 key of instr addrs in ELs 0,1
- bool EnIA = false; // using APIAKey_EL1 key of instr addrs in ELs 0,1
- bool EnIB = false; // using APIBKey_EL1 key of instr addrs in ELs 0,1
+ bool EnDA = true; // using APDAKey_EL1 key of instr addrs in ELs 0,1
+ bool EnDB = true; // using APDBKey_EL1 key of instr addrs in ELs 0,1
+ bool EnIA = true; // using APIAKey_EL1 key of instr addrs in ELs 0,1
+ bool EnIB = true; // using APIBKey_EL1 key of instr addrs in ELs 0,1
/**
* Some registers alias with others, and therefore need to be translated.
InitReg(MISCREG_HACTLR)
.hyp().monNonSecure();
InitReg(MISCREG_HCR)
- .hyp().monNonSecure();
+ .hyp().monNonSecure()
+ .res0(0x90000000);
+ InitReg(MISCREG_HCR2)
+ .hyp().monNonSecure()
+ .res0(0xffa9ff8c);
InitReg(MISCREG_HDCR)
.hyp().monNonSecure();
InitReg(MISCREG_HCPTR)
InitReg(MISCREG_HTPIDR)
.hyp().monNonSecure();
InitReg(MISCREG_CNTFRQ)
- .unverifiable()
- .reads(1).mon();
+ .reads(1)
+ .highest(system)
+ .privSecureWrite(aarch32EL3);
InitReg(MISCREG_CNTKCTL)
.allPrivileges().exceptUserMode();
InitReg(MISCREG_CNTP_TVAL)
.allPrivileges().exceptUserMode().writes(0);
InitReg(MISCREG_ID_AA64MMFR2_EL1)
.allPrivileges().exceptUserMode().writes(0);
+
+ InitReg(MISCREG_APDAKeyHi_EL1)
+ .allPrivileges().exceptUserMode();
+ InitReg(MISCREG_APDAKeyLo_EL1)
+ .allPrivileges().exceptUserMode();
+ InitReg(MISCREG_APDBKeyHi_EL1)
+ .allPrivileges().exceptUserMode();
+ InitReg(MISCREG_APDBKeyLo_EL1)
+ .allPrivileges().exceptUserMode();
+ InitReg(MISCREG_APGAKeyHi_EL1)
+ .allPrivileges().exceptUserMode();
+ InitReg(MISCREG_APGAKeyLo_EL1)
+ .allPrivileges().exceptUserMode();
+ InitReg(MISCREG_APIAKeyHi_EL1)
+ .allPrivileges().exceptUserMode();
+ InitReg(MISCREG_APIAKeyLo_EL1)
+ .allPrivileges().exceptUserMode();
+ InitReg(MISCREG_APIBKeyHi_EL1)
+ .allPrivileges().exceptUserMode();
+ InitReg(MISCREG_APIBKeyLo_EL1)
+ .allPrivileges().exceptUserMode();
+
InitReg(MISCREG_CCSIDR_EL1)
.allPrivileges().exceptUserMode().writes(0);
InitReg(MISCREG_CLIDR_EL1)
.mapsTo(MISCREG_HACTLR);
InitReg(MISCREG_HCR_EL2)
.hyp().mon()
- .mapsTo(MISCREG_HCR /*, MISCREG_HCR2*/);
+ .mapsTo(MISCREG_HCR, MISCREG_HCR2);
InitReg(MISCREG_MDCR_EL2)
.hyp().mon()
.mapsTo(MISCREG_HDCR);
.allPrivileges().exceptUserMode()
.mapsTo(MISCREG_CNTKCTL);
InitReg(MISCREG_CNTFRQ_EL0)
- .reads(1).mon()
+ .reads(1)
+ .highest(system)
+ .privSecureWrite(aarch32EL3)
.mapsTo(MISCREG_CNTFRQ);
InitReg(MISCREG_CNTPCT_EL0)
.reads(1)
.allPrivileges().exceptUserMode()
.mapsTo(MISCREG_ICC_AP0R3);
InitReg(MISCREG_ICC_AP1R0_EL1)
- .banked()
+ .banked64()
.mapsTo(MISCREG_ICC_AP1R0);
InitReg(MISCREG_ICC_AP1R0_EL1_NS)
.bankedChild()
.allPrivileges().exceptUserMode()
.mapsTo(MISCREG_ICC_AP1R0_S);
InitReg(MISCREG_ICC_AP1R1_EL1)
- .banked()
+ .banked64()
.mapsTo(MISCREG_ICC_AP1R1);
InitReg(MISCREG_ICC_AP1R1_EL1_NS)
.bankedChild()
.allPrivileges().exceptUserMode()
.mapsTo(MISCREG_ICC_AP1R1_S);
InitReg(MISCREG_ICC_AP1R2_EL1)
- .banked()
+ .banked64()
.mapsTo(MISCREG_ICC_AP1R2);
InitReg(MISCREG_ICC_AP1R2_EL1_NS)
.bankedChild()
.allPrivileges().exceptUserMode()
.mapsTo(MISCREG_ICC_AP1R2_S);
InitReg(MISCREG_ICC_AP1R3_EL1)
- .banked()
+ .banked64()
.mapsTo(MISCREG_ICC_AP1R3);
InitReg(MISCREG_ICC_AP1R3_EL1_NS)
.bankedChild()
.allPrivileges().exceptUserMode().writes(0)
.mapsTo(MISCREG_ICC_HPPIR1);
InitReg(MISCREG_ICC_BPR1_EL1)
- .banked()
+ .banked64()
.mapsTo(MISCREG_ICC_BPR1);
InitReg(MISCREG_ICC_BPR1_EL1_NS)
.bankedChild()
.secure().exceptUserMode()
.mapsTo(MISCREG_ICC_BPR1_S);
InitReg(MISCREG_ICC_CTLR_EL1)
- .banked()
+ .banked64()
.mapsTo(MISCREG_ICC_CTLR);
InitReg(MISCREG_ICC_CTLR_EL1_NS)
.bankedChild()
.allPrivileges().exceptUserMode()
.mapsTo(MISCREG_ICC_IGRPEN0);
InitReg(MISCREG_ICC_IGRPEN1_EL1)
- .banked()
+ .banked64()
.mapsTo(MISCREG_ICC_IGRPEN1);
InitReg(MISCREG_ICC_IGRPEN1_EL1_NS)
.bankedChild()
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